Circuits, Communications and Systems, Pacific-Asia Conference on (2009)
May 16, 2009 to May 17, 2009
Support vector machines (SVMs) are powerful, state-of-the-art machine learning tools. With the aim to integrate SVM training capability into embedded systems while being able to meet area and performance constraints, a parallel and scalable digital architecture for training SVMs on-line is proposed and implemented on a field-programmable gate array (FPGA). Experiments show that the proposed SVM processor can solve the channel equalization problem effectively with fixed-point arithmetic and exhibits good scalability with respect to the number of cache update units (CUUs). This architecture is particularly suitable to be applied in embedded environments, as designers can easily trade off between area and performance to meet the constraints.
support vector machine (SVM), scalable architecture, field-programmable gate array (FPGA), channel equalization
H. Shen and K. Cao, "Scalable SVM Processor and Its Application to Nonlinear Channel Equalization," 2009 Pacific-Asia Conference on Circuits, Communications and Systems (PACCS 2009)(PACCS), Chengdu, 2009, pp. 206-209.