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2014 Sixth International Symposium on Parallel Architectures, Algorithms and Programming (PAAP) (2014)
Beijing, China
July 13, 2014 to July 15, 2014
ISSN: 2168-3034
ISBN: 978-1-4799-3844-5
pp: 29-34
ABSTRACT
Notice of Violation of IEEE Publication Principles

"Efficient FPGA-Mapping of 1024 point FFT Pipeline SDF Processor"
by Imran Ali Qureshi, Fahad Qureshi, Ghulam Muhammad Shaikh
in the Proceedings of the Sixth Interantional Symposium on Parallel Architectures, Algorithms and Programming, July 2014, pp. 29-34

After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles.

This paper is a duplication of the original text from the paper cited below. The original text was copied prior to submission to IEEE without attribution (including appropriate references to the original author(s) and without permission. Two of the authors, by Imran Ali Qureshi and Ghulam Muhammad Shaikh were responsible for the misconduct.

Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:

"Efficient FPGA-Mapping of Pipeline SDF FFT Processors"
by Carl Ingemarsson, Peter Kallstrom, Fahad Qureshi, Oscar Gustafsson
Submitted to IEEE Transactions on Very Large Scale Integration, March 2015

In this paper the efficient mapping of pipeline single path delay feedback (SDF) fast Fourier transform (FFT) processors to FPGAs is considered. By paying special attention to how the design can efficiently be mapped to the course grained hardware structure of a target field programmable gate array (FPGA) better implementation results can be obtained.This is illustrated by mapping a R22 SDF FFT processor, targeted towards Virtex-4 .The FPGA mapping of these designs have been explored in detail. Algorithmic transformations that provide a better mapping is proposed, resulting in implementation achievements that by far outperform earlier published work.For Virtex-4 the results show a better throughput per slice and lesser latency , still not using more memory or DSP48 resources.
INDEX TERMS
Pipeline processing, Field programmable gate arrays, Table lookup, Adders, Registers, Pipelines, Multiplexing,Single path delay feedback, Fast fourier transform, Field programmable gate array
CITATION
"Notice of Violation of IEEE Publication Principles
Efficient FPGA-mapping of 1024 point FFT Pipeline SDF Processor", 2014 Sixth International Symposium on Parallel Architectures, Algorithms and Programming (PAAP), vol. 00, no. , pp. 29-34, 2014, doi:10.1109/PAAP.2014.70
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