Parallel Architectures, Algorithms and Programming, International Symposium on (2011)
Dec. 9, 2011 to Dec. 11, 2011
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PAAP.2011.70
Advancement in design tools is necessary to bridge the widening productivity gap between hardware design and software development in state-of-the-art Field Programmable Gate Arrays (FPGA). We present a design exploration framework that automatically compiles C applications to realize efficient custom co-processor structures for hardware acceleration on the reconfigurable logic. We show that the proposed design exploration framework can automatically generate Register Transfer Level (RTL) codes from C-functions that outperform the commercial Altera C2H RTL generator by about 40% in terms of average area-time product.
L. M. Chuong, S. Lam, T. Srikanthan, L. C. Soon and Y. L. Aung, "Automatic Compilation of C Applications for FPGA-Based Hardware Acceleration," Parallel Architectures, Algorithms and Programming, International Symposium on(PAAP), Tianjin, China, 2011, pp. 223-227.