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Parallel Architectures, Algorithms and Programming, International Symposium on (2011)
Tianjin, China
Dec. 9, 2011 to Dec. 11, 2011
ISBN: 978-0-7695-4575-2
pp: 203-207
The rapid increase in the complexity of real-life applications has led to the perpetual demand of refined architectural designs. Multiprocessor systems-on-chip (MPSoC) emerges as one of the possible solution for satiating such enormous computational needs. These MPSoCs are employed with Network-On-Chip (NoC) interconnect for power efficient and scalable inter-communication required between processors. Mapping parallelized tasks of applications onto these MPSoCs is the next gigantic problem, which can be done either at design-time or at run-time. However, design-time strategies may sometimes provide a more optimal mapping but they are restricted to predefined set of applications and seem incapable of run-time resource management. On the contrary, run-time mapping techniques overcome this limitation by determining the state of the platform and incorporating resource management before mapping. This paper describes a heuristic for run-time mapping of parallelized tasks of an application considering efficient computation, communication and resource utilization as the main parameters for optimization.
Heterogeneous architectures, Network-on-Chip (NoC), MPSoC design, mapping heuristics

A. K. Singh, W. Jigang, S. Kaushik and T. Srikanthan, "Run-Time Computation and Communication Aware Mapping Heuristic for NoC-Based Heterogeneous MPSoC Platforms," Parallel Architectures, Algorithms and Programming, International Symposium on(PAAP), Tianjin, China, 2011, pp. 203-207.
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