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Parallel Architectures, Algorithms and Programming, International Symposium on (2011)
Tianjin, China
Dec. 9, 2011 to Dec. 11, 2011
ISBN: 978-0-7695-4575-2
pp: 37-41
According to the characteristics of multi-core architectures and binary storage property of integer sequence, this paper proposes an efficient thread-level parallel algorithm for sorting integer sequence on multi-core computers. The algorithm divides the input integer sequence to several data blocks in main memory and distributes these blocks into the shared L2 cache and private L1 cache respectively, implements dynamically load balance among the processing cores, and utilizes data-level parallel SIMD instructions and thread-binding technique to speed up the sorting procedure. Experiment results show that the algorithm can obtain high speedup and good scalability, and its execution efficiency will not be affected by the data distribution of input integer sequence.
Sorting integers; Multi-core computers; Multi-level caches; Thread-level parallelism; Datalevel parallelism; Mapping; Prefix sum

Z. Cheng, K. Qi, L. Jun and H. Yi-Ran, "Thread-Level Parallel Algorithm for Sorting Integer Sequence on Multi-core Computers," Parallel Architectures, Algorithms and Programming, International Symposium on(PAAP), Tianjin, China, 2011, pp. 37-41.
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