Parallel Architectures, Algorithms and Programming, International Symposium on (2010)
Dalian, Liaoning China
Dec. 18, 2010 to Dec. 20, 2010
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PAAP.2010.46
To establish a highly-efficient analytical performance model of routers is crucial for the design of NoC. In this paper, an analytical router performance model which is based on M/D/1/B queuing theory is proposed to analyze various packet blockings at the input buffers during the transfer process, and then a computing method based on Markov chain for flow-control feedback probability is presented to estimate some key metrics in terms of buffer utilization, etc. Compared with BookSim, a famous cycle-accurate NoC simulator, the results show that the average error of the computing method for the flow-control feedback probability is 7.87%.
Network-on-Chip, Markov Chain, queuing theory, performance analysis
W. Zheng, S. Gan, Y. Zhang and X. Dong, "A Performance Analytical Approach Based on Queuing Model for Network-on-Chip," Parallel Architectures, Algorithms and Programming, International Symposium on(PAAP), Dalian, Liaoning China, 2010, pp. 354-359.