Parallel Architectures, Algorithms and Programming, International Symposium on (2010)
Dalian, Liaoning China
Dec. 18, 2010 to Dec. 20, 2010
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/PAAP.2010.59
This paper proposes a fast reconfiguration algorithm for the two-dimensional degradable mesh-connected processor arrays. The proposed algorithm simplifies a dynamic programming approach to construct logical columns. For each processing element lying in the logical columns, the calculation is reduced from five operations (one assignment, two additions and two comparisons) that are taken in the state-of-the-art to single assignment operation in most cases, or three operations (one assignment, one comparison and one addition) in worst case. Simulation results based on same benchmarks utilized in the state-of-the-art show that, the simplified algorithm runs faster by 28%, without loss of harvest. Moreover, the increase of the total interconnection length of the target array is acceptable.
Degradable VLSI array, reconfiguration, routing, fault-tolerance, algorithms
W. Jigang, D. Zhang, J. Wang and Y. Zhang, "Accelerating Reconfiguration for Degradable Mesh-Connected Processor Arrays," Parallel Architectures, Algorithms and Programming, International Symposium on(PAAP), Dalian, Liaoning China, 2010, pp. 55-58.