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11th IEEE International On-Line Testing Symposium (2005)
French Riviera
July 6, 2005 to July 8, 2005
ISBN: 0-7695-2406-0
pp: 69
In this talk, we describe a new paradigm to design in soft error resilience by reusing already existent on-chip DFT resources. For example, scan systems that are required for manufacturing test and debug involve significant circuitry that are used only during post-silicon debug and production testing. These resources are then left unused throughout the entire lifetime of the product as they are not required for normal system operation. These structures continue to occupy additional silicon area and draw additional leakage power. We demonstrate how to reuse these scan resources to enable a built-in soft error resilience (BISER) design paradigm. These circuits result in more than 20 times reduction in soft error rate while incurring a system-level power overhead of 3-5%. Additional power-saving techniques are possible. The BISER techniques produce the best results in terms of power, performance and area overheads (when all 3 attributes are considered) compared to traditional major redundancy techniques. These techniques are also suitable for adaptive applications targeting a wide range of applications (e.g., networking ASICs, microprocessors) with various power, performance and soft error rate trade-offs.
Resilience, Circuit testing, Design for testability, System testing, Error analysis, Manufacturing, Production systems, Silicon, Redundancy, Microprocessors
"DFT assisted built-in soft error resilience", 11th IEEE International On-Line Testing Symposium, vol. 00, no. , pp. 69, 2005, doi:10.1109/IOLTS.2005.23
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