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Network and Parallel Computing Workshops, IFIP International Conference on (2009)
Gold Coast, Australia
Oct. 19, 2009 to Oct. 21, 2009
ISBN: 978-0-7695-3837-2
pp: 16-22
The speed gap between processor and memory is the major bottleneck for modern computing systems. Many modern processors, such as the CELL processor, employ multi-core, multimodule architecture to hide memory access latency. However, making effective use of multiple memory modules remains difficult, considering the combined effect of performance and energy requirements. This paper studies the scheduling and assignment problem that optimize both energy and performance. An efficient algorithm, EALSPP (Energy Aware Loop Scheduling with Prefetching and Partition), is proposed. The algorithm attempts to maximize energy saving while hiding memory latency with the combination of loop scheduling, data prefetching, memory partition, and heterogeneous memory module type assignment. Experimental results demonstrate the effectiveness of our approach.
Energy minimization, loop scheduling, prefetching, partition, multi-module

M. Qiu, L. Wang, M. Liu, S. Liu and F. Hu, "Energy Aware Loop Scheduling for High Performance Multi-Module Memory," Network and Parallel Computing Workshops, IFIP International Conference on(NPC), Gold Coast, Australia, 2009, pp. 16-22.
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