Networks-on-Chip, International Symposium on (2012)
Copenhagen, UT Denmark
May 9, 2012 to May 11, 2012
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/NOCS.2012.19
As in other computer architecture areas, interconnection networks research relies most of the times on simulation tools. This paper announces the release of an open-source tool suitable to be used for accurate modeling from small CMP to large supercomputer interconnection networks. The cycle-accurate modeling of TOPAZ can be used standalone through synthetic traffic patterns and application-traces or within full-system evaluation systems such as GEMS or GEM5 effortlessly. In fact, we provide an advanced interface that enables the replacement of the original lightweight but optimistic GEMS and GEM5 network simulator with limited performance impact on the simulation time. Our tests indicate that in this context, underestimating network modeling could induce up to 50% error in the performance estimation of the simulated system. To minimize the impact of detailed network modeling on simulation time, we incorporate mechanisms able to attenuate the higher computational effort, reducing in this way the slowdown of the full system simulation with accurate performance estimations. Additionally, in order to evaluate large-scale networks, we parallelize the simulator to be able to optimize memory resources with the growing number of cores available per chip in the simulation farms. This allows us to simulate node networks exceeding one million of routers with up to 70% efficiency in a multithreaded simulation running on twelve cores.
simulator, interconnection networks, chip multiprocessor, supercomputer
P. Abad, P. Prieto, L. G. Menezo, J. Gregorio, V. Puente and A. Colaso, "TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers," Networks-on-Chip, International Symposium on(NOCS), Copenhagen, UT Denmark, 2012, pp. 99-106.