The Community for Technology Leaders
Networks-on-Chip, International Symposium on (2009)
La Jolla, CA, USA
May 10, 2009 to May 13, 2009
ISBN: 978-1-4244-4142-6
TABLE OF CONTENTS
Papers

Copyright (PDF)

pp. ii

Table of contents (PDF)

pp. viii-xi

HiRA: A methodology for deadlock free routing in hierarchical networks on chip (Abstract)

Andres Mejia , Dept. of Computing Engineering, Technical University of Valencia, Spain
Maurizio Palesi , Dept. of Computer Science and Telecommunications Engineering, University of Catania, Italy
Rickard Holsmark , Dept. of Electronics and Computer Engineering, Jönköping University, Sweden
Shashi Kumar , Dept. of Electronics and Computer Engineering, Jönköping University, Sweden
pp. 2-11

Using adaptive routing to compensate for performance heterogeneity (Abstract)

Yatish Patel , University of California, Berkeley, USA
John Wawrzynek , University of California, Berkeley, USA
Yury Markovsky , University of California, Berkeley, USA
pp. 12-21

Fault-tolerant architecture and deflection routing for degradable NoC switches (Abstract)

Martin Radetzki , Institut für Technische Informatik, Universität Stuttgart, Germany
Adan Kohler , Institut für Technische Informatik, Universität Stuttgart, Germany
pp. 22-31

Adaptive stochastic routing in fault-tolerant on-chip networks (Abstract)

Jose Luis Nunez-Yanez , Department of Electrical and Electronic Engineering, Bristol University, BS8 1UB UK
Sohini Dasgupta , School of Computer Science, University of Manchester, M13 9PL UK
Doug Edwards , School of Computer Science, University of Manchester, M13 9PL UK
Wei Song , School of Computer Science, University of Manchester, M13 9PL UK
pp. 32-37

Static virtual channel allocation in oblivious routing (Abstract)

G. Edward Suh , Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA
Tina Wen , Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA
Srinivas Devadas , Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA
Myong Hyon Cho , Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA
Michel Kinsy , Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA
Keun Sup Shim , Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA
Mieszko Lis , Computer Science and Artificial Intelligence Laboratory, Massachusetts Institute of Technology, USA
pp. 38-43

Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip (Abstract)

Wenhua Dou , School of Computer Science, National University of Defense Technology, China
Yue Qian , School of Computer Science, National University of Defense Technology, China
Zhonghai Lu , Dept. of Electronic, Computer and Software Systems, Royal Institute of Technology (KTH), Sweden
pp. 44-53

Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links (Abstract)

David Wolpert , Dept. of Electrical and Computer Engineering, University of Rochester, NY 14627, USA
Paul Ampadu , Dept. of Electrical and Computer Engineering, University of Rochester, NY 14627, USA
Bo Fu , Dept. of Electrical and Computer Engineering, University of Rochester, NY 14627, USA
pp. 54-63

Recursive partitioning multicast: A bandwidth-efficient routing for Networks-on-Chip (Abstract)

Lei Wang , Department of Computer Science and Engineering, Texas A&M University, College Station, 77843 USA
Yuho Jin , Department of Computer Science and Engineering, Texas A&M University, College Station, 77843 USA
Eun Jung Kim , Department of Computer Science and Engineering, Texas A&M University, College Station, 77843 USA
Hyungjun Kim , Department of Computer Science and Engineering, Texas A&M University, College Station, 77843 USA
pp. 64-73

Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus (Abstract)

T. El-Ghazawi , HPCL, GWU, Washington DC. 20052, USA
S. Suboh , HPCL, GWU, Washington DC. 20052, USA
M. Bakhouya , UTBM, 90010 Belfort, France
J. Gaber , UTBM, 90010 Belfort, France
pp. 74-79

Energy efficient application mapping to NoC processing elements operating at multiple voltage levels (Abstract)

Alexander Hall , Department of EECS, UC Berkeley, CA, USA
Pavel Ghosh , Department of Computer Science and Engineering, Arizona State University, Tempe, USA
Arunabha Sen , Department of Computer Science and Engineering, Arizona State University, Tempe, USA
pp. 80-85

The design of a latency constrained, power optimized NoC for a 4G SoC (Abstract)

Avinoam Kolodny , Electrical Engineering Department, Technion - Israel Institute of Technology, Haifa 32000, Israel
Rudy Beraha , Qualcomm Corp. Research and Development, San Diego, California 92121, USA
Isask'har Walter , Electrical Engineering Department, Technion - Israel Institute of Technology, Haifa 32000, Israel
Israel Cidon , Electrical Engineering Department, Technion - Israel Institute of Technology, Haifa 32000, Israel
pp. 86

Performance Evaluation of NoC Architectures for Parallel Workloads (Abstract)

Philippe O. A. Navaux , Informatics Institute, Universidade Federal do Rio Grande do Sul, RS, Brazil
Lucas M. Schnorr , Informatics Institute, Universidade Federal do Rio Grande do Sul, RS, Brazil
Marco A. Z. Alves , Informatics Institute, Universidade Federal do Rio Grande do Sul, RS, Brazil
pp. 87

Packet-level static timing analysis for NoCs (Abstract)

Isask'har Walter , Department of Electrical Engineering, Technion-Israel Institute of Technology, Israel
Isaac Keslassy , Department of Electrical Engineering, Technion-Israel Institute of Technology, Israel
Avinoam Kolodny , Department of Electrical Engineering, Technion-Israel Institute of Technology, Israel
Evgeni Krimer , Department of Electrical and Computer Engineering, University of Texas at Austin, USA
Mattan Erez , Department of Electrical and Computer Engineering, University of Texas at Austin, USA
pp. 88

Increasing NoC power estimation accuracy through a rate-based model (Abstract)

Thiago R. da Rosa , PUCRS, Av. Ipiranga 6681, P. 32, Porto Alegre, Brazil
Cezar Reinbrecht , PUCRS, Av. Ipiranga 6681, P. 32, Porto Alegre, Brazil
Guilherme Guindani , PUCRS, Av. Ipiranga 6681, P. 32, Porto Alegre, Brazil
Fernando Moraes , PUCRS, Av. Ipiranga 6681, P. 32, Porto Alegre, Brazil
pp. 89

On-Chip photonic interconnects for scalable multi-core architectures (Abstract)

Avinash Karanth Kodi , School of Electrical Engineering and Computer Science, Ohio University, Athens, 45701, USA
Xiang Zhang , Electrical and Computer Engineering, University of Arizona, Tucson, 85721, USA
Randy Morris , School of Electrical Engineering and Computer Science, Ohio University, Athens, 45701, USA
Ahmed Louri , Electrical and Computer Engineering, University of Arizona, Tucson, 85721, USA
pp. 90

A Modeling and exploration framework for interconnect network design in the nanometer era (Abstract)

Fred Chen , Department of EECS, Massachusetts Institute of Technology, Cambridge, USA
Ajay Joshi , Department of EECS, Massachusetts Institute of Technology, Cambridge, USA
Vladimir Stojanovic , Department of EECS, Massachusetts Institute of Technology, Cambridge, USA
pp. 91

Power reduction through physical placement of asynchronous routers (Abstract)

Kenneth Stevens , University of Utah, USA
Daniel Gebhardt , University of Utah, USA
pp. 92

Networks-on-chip in emerging interconnect paradigms: Advantages and challenges (Abstract)

Yuan Xie , Pennsylvania State University, USA
Partha Pande , Washington State University, USA
Luca P. Carloni , Columbia University, USA
pp. 93-102

Analysis of photonic networks for a chip multiprocessor using scientific applications (Abstract)

Keren Bergman , Lightwave Research Laboratory, Columbia University, New York, 10027, USA
Gilbert Hendry , Lightwave Research Laboratory, Columbia University, New York, 10027, USA
Ankit Jain , Computer Science Department, University of California, Berkeley, 94720, USA
Aleksandr Biberman , Lightwave Research Laboratory, Columbia University, New York, 10027, USA
Leonid Oliker , CRD/NERSC, Lawrence Berkeley National Laboratory, Berkeley, CA 94720, USA
John Shalf , CRD/NERSC, Lawrence Berkeley National Laboratory, Berkeley, CA 94720, USA
Luca P. Carloni , Computer Science Department, Columbia University, New York, 10027, USA
Benjamin G. Lee , Lightwave Research Laboratory, Columbia University, New York, 10027, USA
John Kubiatowicz , Computer Science Department, University of California, Berkeley, 94720, USA
Marghoob Mohiyuddin , Computer Science Department, University of California, Berkeley, 94720, USA
Johnnie Chan , Lightwave Research Laboratory, Columbia University, New York, 10027, USA
Shoaib Kamil , Computer Science Department, University of California, Berkeley, 94720, USA
pp. 104-113

Scalability of network-on-chip communication architecture for 3-D meshes (Abstract)

Axel Jantsch , School of Information and Communication Technologies, Department of Electronics, Computer, and Software Systems, KTH Royal Institute of Technology, Electrum 229, Kista SE 16440, Sw
Awet Yemane Weldezion , School of Information and Communication Technologies, Department of Electronics, Computer, and Software Systems, KTH Royal Institute of Technology, Electrum 229, Kista SE 16440, Sw
Roshan Weerasekera , Centre for Microsystems Engineering, Department of Engineering, Lancaster University, LA1 4YW, UK
Dinesh Pamunuwa , Centre for Microsystems Engineering, Department of Engineering, Lancaster University, LA1 4YW, UK
Hannu Tenhunen , Centre for Microsystems Engineering, Department of Engineering, Lancaster University, LA1 4YW, UK
Matt Grange , Centre for Microsystems Engineering, Department of Engineering, Lancaster University, LA1 4YW, UK
Zhonghai Lu , School of Information and Communication Technologies, Department of Electronics, Computer, and Software Systems, KTH Royal Institute of Technology, Electrum 229, Kista SE 16440, Sw
pp. 114-123

Silicon-photonic clos networks for global on-chip communication (Abstract)

Krste Asanovic , Department of EECS, University of California, Berkeley, USA
Christopher Batten , Department of EECS, Massachusetts Institute of Technology, Cambridge, USA
Yong-Jin Kwon , Department of EECS, University of California, Berkeley, USA
Vladimir Stojanovic , Department of EECS, Massachusetts Institute of Technology, Cambridge, USA
Imran Shamim , Department of EECS, Massachusetts Institute of Technology, Cambridge, USA
Ajay Joshi , Department of EECS, Massachusetts Institute of Technology, Cambridge, USA
Scott Beamer , Department of EECS, University of California, Berkeley, USA
pp. 124-133

Contention-free on-chip routing of optical packets (Abstract)

Somayyeh Koohi , Sharif University of Technology, Tehran, Iran
Shaahin Hessabi , Sharif University of Technology, Tehran, Iran
pp. 134-143

Connection-centric network for spiking neural networks (Abstract)

Robin Emery , Newcastle University, UK
Graeme Chester , Newcastle University, UK
Alex Yakovlev , Newcastle University, UK
pp. 144-152

A Communication and configuration controller for NoC based reconfigurable data flow architecture (Abstract)

Pascal Vivet , CEA, LETI, MINATEC, F38054 GRENOBLE Cedex 9, FRANCE
Fabien Clermidy , CEA, LETI, MINATEC, F38054 GRENOBLE Cedex 9, FRANCE
Yvain Thonnart , CEA, LETI, MINATEC, F38054 GRENOBLE Cedex 9, FRANCE
Romain Lemaire , CEA, LETI, MINATEC, F38054 GRENOBLE Cedex 9, FRANCE
pp. 153-162

Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions (Abstract)

Martti Forsell , VTT, Platform Architectures, Box 1100, FI-90571 Oulu, Finland
pp. 163-172

Best of both worlds: A bus enhanced NoC (BENoC) (Abstract)

Isask'har Walter , Electrical Engineering Department, Technion - Israel Institute of Technology, Israel
Ran Manevich , Electrical Engineering Department, Technion - Israel Institute of Technology, Israel
Avinoam Kolodny , Electrical Engineering Department, Technion - Israel Institute of Technology, Israel
Israel Cidon , Electrical Engineering Department, Technion - Israel Institute of Technology, Israel
pp. 173-182

Flow-aware allocation for on-chip networks (Abstract)

Arnab Banerjee , Computer Laboratory, University of Cambridge, USA
Simon W. Moore , Computer Laboratory, University of Cambridge, USA
pp. 183-192

CTC: An end-to-end flow control protocol for multi-core systems-on-chip (Abstract)

Luca P. Carloni , Computer Science Department, Columbia University in the City of New York, USA
Luciano Bononi , Dipartimento di Scienze dell'Informazione, Università di Bologna, Italy
Michael Soulie , ST Microelectronics, Grenoble, France
Nicola Concer , Dipartimento di Scienze dell'Informazione, Università di Bologna, Italy
Riccardo Locatelli , ST Microelectronics, Grenoble, France
pp. 193-202

Performance and power efficient on-chip communication using adaptive virtual point-to-point connections (Abstract)

Arash Tavakkol , Sharif University of Technology, Tehran, Iran
Hamid Sarbazi-Azad , Sharif University of Technology, Tehran, Iran
Mehdi Modarressi , Sharif University of Technology, Tehran, Iran
pp. 203-212

A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network (Abstract)

Dean N. Truong , Department of Electrical and Computer Engineering, University of California - Davis, USA
Anh T. Tran , Department of Electrical and Computer Engineering, University of California - Davis, USA
Bevan M. Baas , Department of Electrical and Computer Engineering, University of California - Davis, USA
pp. 214-223

A modular synchronizing FIFO for NoCs (Abstract)

Tarik Ono , Sun Microsystems, USA
Mark Greenstreet , University of British Columbia, Canada
pp. 224-233

Estimating reliability and throughput of source-synchronous wave-pipelined interconnect (Abstract)

Mark R. Greenstreet , University of British Columbia, Vancouver, Canada
Paul Teehan , University of British Columbia, Vancouver, Canada
Guy G.F. Lemieux , University of British Columbia, Vancouver, Canada
pp. 234-243

Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture (Abstract)

Georgi N. Gaydadjiev , Computer Engineering Lab., Delft University of Technology, The Netherlands
Luca Benini , Computer Engineering Lab., Delft University of Technology, The Netherlands
Daniele Ludovici , Computer Engineering Lab., Delft University of Technology, The Netherlands
Alessandro Strano , ENDIF, University of Ferrara, 44100, Italy
Davide Bertozzi , DEIS, University of Bologna, 40136, Italy
pp. 244-249

Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers (Abstract)

Young Hoon Kang , University of Southern California / Information Sciences Institute, USA
Jeff Draper , University of Southern California / Information Sciences Institute, USA
Taek-Jun Kwon , University of Southern California / Information Sciences Institute, USA
pp. 250-255

Diagnosis of interconnect shorts in mesh NoCs (Abstract)

Fernanda Lima Kastensmidt , Universidade Federal do Rio Grande do Sul, PPGC - PGMICRO - Instituto de Informática / Escola de Engenharia, P.O. Box 15064, ZIP 91501-970, Porto Alegre, Brazil
Erika Cota , Universidade Federal do Rio Grande do Sul, PPGC - PGMICRO - Instituto de Informática / Escola de Engenharia, P.O. Box 15064, ZIP 91501-970, Porto Alegre, Brazil
Marcelo Lubaszewski , Universidade Federal do Rio Grande do Sul, PPGC - PGMICRO - Instituto de Informática / Escola de Engenharia, P.O. Box 15064, ZIP 91501-970, Porto Alegre, Brazil
Marcos Herve , Universidade Federal do Rio Grande do Sul, PPGC - PGMICRO - Instituto de Informática / Escola de Engenharia, P.O. Box 15064, ZIP 91501-970, Porto Alegre, Brazil
pp. 256-265

BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel (Abstract)

Yueh-Chi Lin , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, ROC
Yu-Hen Hu , Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI53706, USA
Sao-Jie Chen , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, ROC
Ying-Cherng Lan , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, ROC
Shih-Hsin Lo , Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, ROC
pp. 266-275

Exploring concentration and channel slicing in on-chip network router (Abstract)

John Kim , KAIST, Daejeon, Korea
Prabhat Kumar , Northwestern University, 2145 Sheridan Road, Evanston, IL, USA
Gokhan Memik , Northwestern University, 2145 Sheridan Road, Evanston, IL, USA
Alok Choudhary , Northwestern University, 2145 Sheridan Road, Evanston, IL, USA
Yan Pan , Northwestern University, 2145 Sheridan Road, Evanston, IL, USA
pp. 276-285

Author index (PDF)

pp. 286-287
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