The Community for Technology Leaders
Networks-on-Chip, International Symposium on (2007)
Princeton, New Jersey
May 7, 2007 to May 9, 2007
ISBN: 0-7695-2773-6
TABLE OF CONTENTS
Introduction

Committees (PDF)

pp. x
Tutorial: Networks on Chips

Tooling, OS Services and Middleware (PDF)

Luca Benini , U. Bologna, Italy
pp. null
Keynote 1
Session 1: NoC Design Case Studies

Implementation and Evaluation of a Dynamically Routed Processor Operand Network (Abstract)

Robert McDonald , The University of Texas at Austin, USA
Paul Gratz , The University of Texas at Austin, USA
Heather Hanson , The University of Texas at Austin, USA
Karthikeyan Sankaralingam , The University of Texas at Austin, USA
Stephen W. Keckler , The University of Texas at Austin, USA
Doug Burger , The University of Texas at Austin, USA
Premkishore Shivakumar , The University of Texas at Austin, USA
pp. 7-17

On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus (Abstract)

Thomas William Ainsworth , University of Southern California Los Angeles, USA
Timothy Mark Pinkston , University of Southern California Los Angeles, USA
pp. 18-29

Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC (Abstract)

Joo-Young Kim , Korea Advanced Institute of Science and Technology (KAIST), Korea
Kwanho Kim , Korea Advanced Institute of Science and Technology (KAIST), Korea
Hoi-Jun Yoo , Korea Advanced Institute of Science and Technology (KAIST), Korea
Seung-Jin Lee , Korea Advanced Institute of Science and Technology (KAIST), Korea
Donghyun Kim , Korea Advanced Institute of Science and Technology (KAIST), Korea
pp. 30-39

Architecture of the Scalable Communications Core (Abstract)

Aliaksei Chapyzhenka , Intel Corporation, California, USA
Jeff Hoffman , Intel Corporation, California, USA
Anthony Chun , Intel Corporation, California, USA
David Arditti Ilitzky , Intel Corporation, California, USA
pp. 40-52
Session 2: Technology and Circuit Technologies

On the Design of a Photonic Network-on-Chip (Abstract)

Assaf Shacham , Columbia University, USA
Luca P. Carloni , Columbia University, USA
Keren Bergman , Columbia University, USA
pp. 53-64

NoC Communication Strategies Using Time-to-Digital Conversion (Abstract)

David Kinniment , Newcastle University, UK
Keith Heron , Newcastle University, UK
Alex Yakovlev , Newcastle University, UK
Nikolaos Minas , Newcastle University, UK
Crescenzo D'Alessandro , Newcastle University, UK
pp. 65-74

A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs (Abstract)

Shuming Chen , National University of Defense Technology, China
Xiangyuan Liu , National University of Defense Technology, China
pp. 75-82

Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures (Abstract)

Alain Greiner , The University of Pierre and Marie Curie, France
Ivan Miro Panades , STMicroelectronics, France
pp. 83-94
Session 3: System Architecture, Verification and Debug

Transaction-Based Communication-Centric Debug (Abstract)

Kees Goossens , NXP Semiconductors, The Netherlands; Technical University Delft, The Netherlands
Bart Vermeulen , NXP Semiconductors, The Netherlands
Remco van Steeden , Technical University of Twente, The Netherlands
Martijn Bennebroek , Research, Philips, The Netherlands
pp. 95-106

The Impact of Higher Communication Layers on NoC Supported MP-SoCs (Abstract)

H. Corporaal , Technical University Eindhoven, The Netherlands
T. Marescaux , IMEC, Belgium
E. Brockmeyer , IMEC, Belgium
pp. 107-116

The Power of Priority: NoC Based Distributed Cache Coherency (Abstract)

Evgeny Bolotin , Israel Institute of Technology, Israel
Avinoam Kolodny , Israel Institute of Technology, Israel
Zvika Guz , Israel Institute of Technology, Israel
Israel Cidon , Israel Institute of Technology, Israel
Ran Ginosar , Israel Institute of Technology, Israel
pp. 117-126

A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study (Abstract)

Julien Schmaltz , Saarland University, Germany
Dominique Borrione , TIMA Laboratory-INPG, France
Amr Helmy , TIMA Laboratory-INPG, France
Laurence Pierre , TIMA Laboratory-INPG, France
pp. 127-136

Access Regulation to Hot-Modules in Wormhole NoCs (Abstract)

Israel Cidon , Israel Institute of Technology, Israel
Avinoam Kolodny , Israel Institute of Technology, Israel
Ran Ginosar , Israel Institute of Technology, Israel
Isask'har Walter , Israel Institute of Technology, Israel
pp. 137-148
Keynote 2
Session 4: Routing and Topology

Approaching Ideal NoC Latency with Pre-Configured Routes (Abstract)

Dionisios Pnevmatikatos , Institute of Computer Science, Foundation for Research & Technology-Hellas (FORTH), Greece
George Michelogiannakis , Institute of Computer Science, Foundation for Research & Technology-Hellas (FORTH), Greece
Manolis Katevenis , Institute of Computer Science, Foundation for Research & Technology-Hellas (FORTH), Greece
pp. 153-162

A Power and Energy Exploration of Network-on-Chip Architectures (Abstract)

Arnab Banerjee , University of Cambridge, UK
Robert Mullins , University of Cambridge, UK
Simon Moore , University of Cambridge, UK
pp. 163-172

A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing (Abstract)

K.P. Lam , The Chinese University of Hong Kong, Hong Kong
Wayne Luk , Imperial College London, UK
Terrence S.T. Mak , Imperial College London, UK
Peter Y.K. Cheung , Imperial College London, UK
Pete Sedcole , Imperial College London, UK
pp. 173-182

Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips (Abstract)

J. Duato , Universidad Politecnica de Valencia, Spain
J. Flich , Universidad Politecnica de Valencia, Spain
P. Lopez , Universidad Politecnica de Valencia, Spain
A. Mejia , Universidad Politecnica de Valencia, Spain
pp. 183-194

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing (Abstract)

S. Bourduas , McGill University, Canada
Z. Zilic , McGill University, Canada
pp. 195-204
Panel Session

Towards Open Network-on-Chip Benchmarks (Abstract)

Erno Salminen , Tampere University of Technology
Axel Jantsch , Royal Institute of Technology
Partha Pande , Washington State University
Andre Ivanov , University of British Columbia
Cristian Grecu , University of British Columbia
Umit Ogras , Carnegie Mellon University
Radu Marculescu , Carnegie Mellon University
pp. 205
Poster Session

An Analytical Approach for Dimensioning Mixed Traffic Networks (PDF)

Per Badlund , Royal Institute of Technology, Sweden
Axel Jantsch , Royal Institute of Technology, Sweden
pp. 215

Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip (PDF)

Xuan-Tu Tran , CEA-LETI, France
Francois Bertrand , CEA-LETI, France
Chantal Robach , INPG-LCIS, France
Yvain Thonnart , CEA-LETI, France
Vincent Beroulle , INPG-LCIS, France
Jean Durupt , CEA-LETI, France
pp. 216

A Study of NoC Exit Strategies (PDF)

Axel Jantsch , KTH-Royal Institute of Technology, Sweden
Mikael Millberg , KTH-Royal Institute of Technology, Sweden
pp. 217

QNoC Asynchronous Router with Dynamic Virtual Channel Allocation (PDF)

Israel Cidon , Israel Institute of Technology, Israel
Ran Ginosar , Israel Institute of Technology, Israel
Rostislav (Reuven) Dobkin , Israel Institute of Technology, Israel
pp. 218

Reducing Interconnect Cost in NoC through Serialized Asynchronous Links (PDF)

Luca Benini , University of Bologna
Simon Ogg , University of Southampton, UK
Crescenzo D'Alessandro , Newcastle University, UK
Alex Yakovlev , Newcastle University, UK
Enrico Valli , University of Bologna
Bashir Al-Hashimi , University of Southampton, UK
pp. 219

Thermal Impacts on NoC Interconnects (PDF)

Ibis Benito , University of Massachusetts Amherst, USA
Sheng Xu , University of Massachusetts Amherst, USA
Wayne Burleson , University of Massachusetts Amherst, USA
pp. 220
Session 5: Reconfigurable NoCs

NOC-centric Security of Reconfigurable SoC (Abstract)

Emmanuel Juin , Universite de Bretagne Sud/CNRS, France
Jean-Philippe Diguet , Universite de Bretagne Sud/CNRS, France
Samuel Evain , Universite de Bretagne Sud/CNRS, France
Guy Gogniat , Universite de Bretagne Sud/CNRS, France
Romain Vaslin , Universite de Bretagne Sud/CNRS, France
pp. 223-232

Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases (Abstract)

Kees Goossens , Delft University of Technology, The Netherlands; NXP Semiconductors, The Netherlands
Andreas Hansson , Eindhoven University of Technology, The Netherlands
pp. 233-242

Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances (Abstract)

Hayder Mrabet , LIP6, Universite Pierre et Marie Curie, France
Christian Masson , LIP6, Universite Pierre et Marie Curie, France
Habib Mehrez , LIP6, Universite Pierre et Marie Curie, France
Zied Marrakchi , LIP6, Universite Pierre et Marie Curie, France
pp. 243-252

NoC-Based FPGA: Architecture and Routing (Abstract)

Roman Gindin , Israel Institute of Technology, Israel
Israel Cidon , Israel Institute of Technology, Israel
Idit Keidar , Israel Institute of Technology, Israel
pp. 253-264
Dinner Speaker
Keynote 3

NoC: Network or Chip? (PDF)

Israel Cidon , Israel Institute of Technology, Israel
pp. 269
Session 6: CAD and Methodology for NoCs

NoC Design and Implementation in 65nm Technology (Abstract)

Luca Benini , University of Bologna, Italy
Luigi Raffo , University of Cagliari, Italy
Paolo Meloni , University of Cagliari, Italy
Federico Angiolini , University of Bologna, Italy
Giovanni De Micheli , LSI, EPFL, Switzerland
Srinivasan Murali , Stanford University, California, USA
Antonio Pullini , Politecnico di Torino, Italy
David Atienza , LSI, EPFL, Switzerland; Complutense University, Spain
pp. 273-282

Implications of Rent's Rule for NoC Design and Its Fault-Tolerance (Abstract)

Daniel Greenfield , University of Cambridge, UK
Jeong-Gun Lee , University of Cambridge, UK
Arnab Banerjee , University of Cambridge, UK
Simon Moore , University of Cambridge, UK
pp. 283-294

ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC (Abstract)

Yvain Thonnart , CEA-LETI, France
Pascal Vivet , CEA-LETI, France
Cedric Koch-Hofer , TIMA Laboratory, France
Marc Renaudin , TIMA Laboratory, France
pp. 295-306
Session 7: NoC Mapping and Simulation

Implementing DSP Algorithms with On-Chip Networks (Abstract)

Yehia Massoud , Rice University
Adnan Aziz , UT Austin
Tamer Ragheb , Rice University
Xiang Wu , AMD
pp. 307-316

A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network (Abstract)

An-Yeu (Andy) Wu , National Taiwan University, Taiwan
Chih-Hao Chao , National Taiwan University, Taiwan
Yu-Kuang Lien , National Taiwan University, Taiwan
Wein-Tsung Shen , National Taiwan University, Taiwan
pp. 317-322

Fast, Accurate and Detailed NoC Simulations (Abstract)

Pascal T. Wolkotte , University of Twente, The Netherlands
Gerard J.M. Smit , University of Twente, The Netherlands
Philip K.F. Holzenspies , University of Twente, The Netherlands
pp. 323-332
Author Index

Author Index (PDF)

pp. 333
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