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Networks-on-Chip, International Symposium on (2007)
Princeton, New Jersey
May 7, 2007 to May 9, 2007
ISBN: 0-7695-2773-6
pp: 273-282
Antonio Pullini , Politecnico di Torino, Italy
Federico Angiolini , University of Bologna, Italy
Paolo Meloni , University of Cagliari, Italy
David Atienza , LSI, EPFL, Switzerland; Complutense University, Spain
Srinivasan Murali , Stanford University, California, USA
Luigi Raffo , University of Cagliari, Italy
Giovanni De Micheli , LSI, EPFL, Switzerland
Luca Benini , University of Bologna, Italy
ABSTRACT
As embedded computing evolves towards ever more pow- erful architectures, the challenge of properly interconnect- ing large numbers of on-chip computation blocks is becom- ing prominent. Networks-on-Chip (NoCs) have been pro- posed as a scalable solution to both physical design issues and increasing bandwidth demands. However, this claim has not been fully validated yet, since the design properties and tradeoffs of NoCs have not been studied in detail below the 100 nm threshold. <p>This work is aimed at shedding light on the opportunities and challenges, both expected and unexpected, of NoC de- sign in nanometer CMOS. We present fully working 65 nm NoC designs, a complete NoC synthesis flow and detailed scalability analysis.</p>
INDEX TERMS
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CITATION

L. Benini et al., "NoC Design and Implementation in 65nm Technology," 2007 International Symposium on Networks-on-Chip(NOCS), Princeton, NJ, 2007, pp. 273-282.
doi:10.1109/NOCS.2007.30
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