Networks-on-Chip, International Symposium on (2007)
Princeton, New Jersey
May 7, 2007 to May 9, 2007
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/NOCS.2007.31
Roman Gindin , Israel Institute of Technology, Israel
Israel Cidon , Israel Institute of Technology, Israel
Idit Keidar , Israel Institute of Technology, Israel
We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instances with good performance and low cost. Our architecture minimizes the cost of supporting a wide range of design instances with given throughput requirements by balancing the amount of efficient hard-coded NoC infrastructure and the allocation of "soft" networking resources at configuration time. Although traffic patterns are design-specific, the physical link infrastructure is a performance bottleneck, and hence should be hard-coded. It is therefore important to employ routing schemes that allow for high flexibility to efficiently accommodate different traffic patterns during configuration. We examine the required capacity allocation for supporting a collection of typical traffic patterns on such chips under a number of routing schemes. We propose a new routing scheme, Weighted Ordered Toggle (WOT), and show that it allows high design flexibility with low infrastructure cost. Moreover, WOT utilizes simple, small-area, on-chip routers, and has low memory demands.
R. Gindin, I. Cidon and I. Keidar, "NoC-Based FPGA: Architecture and Routing," 2007 International Symposium on Networks-on-Chip(NOCS), Princeton, NJ, 2007, pp. 253-264.