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Networks-on-Chip, International Symposium on (2007)
Princeton, New Jersey
May 7, 2007 to May 9, 2007
ISBN: 0-7695-2773-6
pp: 216
Xuan-Tu Tran , CEA-LETI, France
Jean Durupt , CEA-LETI, France
Yvain Thonnart , CEA-LETI, France
Francois Bertrand , CEA-LETI, France
Vincent Beroulle , INPG-LCIS, France
Chantal Robach , INPG-LCIS, France
ABSTRACT
The Network-on-Chip (NoC) paradigm has recently emerged as an alternative solution for on-chip communications of the next System-on-Chip (SoC) generation. The advantages of NoC-based systems are numerous: high scalability and versatility, high throughput with good power efficiency,. . . The NoC distributed communication architecture is perfectly adapted to the Globally Asynchronous Locally Synchronous (GALS) platforms where the NoC nodes and links are implemented using asynchronous logic while the computational resources (i.e., IPs) are implemented with standard synchronous design methodologies.
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CITATION

X. Tran, F. Bertrand, C. Robach, Y. Thonnart, V. Beroulle and J. Durupt, "Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip," 2007 International Symposium on Networks-on-Chip(NOCS), Princeton, NJ, 2007, pp. 216.
doi:10.1109/NOCS.2007.24
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