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Networks-on-Chip, International Symposium on (2007)
Princeton, New Jersey
May 7, 2007 to May 9, 2007
ISBN: 0-7695-2773-6
pp: 183-194
J. Flich , Universidad Politecnica de Valencia, Spain
A. Mejia , Universidad Politecnica de Valencia, Spain
P. Lopez , Universidad Politecnica de Valencia, Spain
J. Duato , Universidad Politecnica de Valencia, Spain
ABSTRACT
The design of scalable and reliable interconnection networks for System on Chips (SoCs) introduce new design constraints not present in current multicomputer systems. Although regular topologies are preferred for building NoCs, heterogeneous blocks, fabrication faults and reliability issues derived from the high integration scale may lead to irregular topologies. In this situation, efficient routing becomes a challenge. Although table-based routing allows the use of most routing algorithms on any topology, it does not scale in terms of latency and area. <p>In this paper we propose the region-based routing mechanism that avoids the scalability problems of table-based solutions. From an initial topology and routing algorithm, the mechanism groups, at every switch, destinations into different regions based on the output ports. By doing this, redundant routing information typically found in routing tables is eliminated. Evaluation results show that the mechanism requires only four regions to support several routing algorithms in a 2D mesh with no performance degradation. Moreover, when dealing with link failures, our results indicate that the mechanism combined with the Segment-Based Routing algorithm is able to pack all the routing information into eight regions providing high throughput. The paper provides also a simple and efficient hardware implementation of the mechanism requiring only 240 logic gates per switch to support eight regions in a 2D mesh topology.</p>
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CITATION

J. Duato, J. Flich, P. Lopez and A. Mejia, "Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips," 2007 International Symposium on Networks-on-Chip(NOCS), Princeton, NJ, 2007, pp. 183-194.
doi:10.1109/NOCS.2007.39
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