Networks-on-Chip, International Symposium on (2007)
Princeton, New Jersey
May 7, 2007 to May 9, 2007
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/NOCS.2007.35
Assaf Shacham , Columbia University, USA
Keren Bergman , Columbia University, USA
Luca P. Carloni , Columbia University, USA
Recent remarkable advances in nanoscale silicon-photonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the unique capabilities of optical technologies in the on-chip communications infrastructure. Based on these nano-photonic building blocks, we consider a photonic network-on-chip architecture designed to exploit the enormous transmission bandwidths, low latencies, and low power dissipation enabled by data exchange in the optical domain. The novel architectural approach employs a broadband photonic circuit-switched network driven in a distributed fashion by an electronic overlay control network which is also used for independent exchange of short messages. We address the critical network design issues for insertion in chip multiprocessors (CMP) applications, including topology, routing algorithms, path-setup and teardown procedures, and deadlock avoidance. Simulations show that this class of photonic networks-on-chip offers a significant leap in the performance for CMP intrachip communication systems delivering low-latencies and ultra-high throughputs per core while consuming minimal power.
A. Shacham, L. P. Carloni and K. Bergman, "On the Design of a Photonic Network-on-Chip," 2007 International Symposium on Networks-on-Chip(NOCS), Princeton, NJ, 2007, pp. 53-64.