Networks-on-Chip, International Symposium on (2007)
Princeton, New Jersey
May 7, 2007 to May 9, 2007
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/NOCS.2007.23
Paul Gratz , The University of Texas at Austin, USA
Karthikeyan Sankaralingam , The University of Texas at Austin, USA
Heather Hanson , The University of Texas at Austin, USA
Premkishore Shivakumar , The University of Texas at Austin, USA
Robert McDonald , The University of Texas at Austin, USA
Stephen W. Keckler , The University of Texas at Austin, USA
Doug Burger , The University of Texas at Austin, USA
Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets, tight coupling between processor microarchitecture and network architecture is one of the keys to improving processor performance. This paper presents the design, implementation and evaluation of the TRIPS operand network (OPN). The TRIPS OPN is a 5x5, dynamically routed, 2D mesh micronet that is integrated into the TRIPS microprocessor core. The TRIPS OPN is used for operand passing, register file I/O, and primary memory system I/O. We discuss in detail the OPN design, including the unique features that arise from its integration with the processor core, such as its connection to the execution unit?s wakeup pipeline and its in flight mis-speculated traffic removal. We then evaluate the performance of the network under synthetic and realistic loads. Finally, we assess the processor performance implications of OPN design decisions with respect to the end-to-end latency of OPN packets and the OPN?s bandwidth.
R. McDonald et al., "Implementation and Evaluation of a Dynamically Routed Processor Operand Network," 2007 International Symposium on Networks-on-Chip(NOCS), Princeton, NJ, 2007, pp. 7-17.