The Community for Technology Leaders
2009 2nd International Workshop on Network on Chip Architectures (NoCArc 2009) (2009)
New York, NY
Dec. 12, 2009 to Dec. 12, 2009
ISBN: 978-1-60558-774-5
TABLE OF CONTENTS

Message from the Chairs (Abstract)

Maurizio Palesi , University of Catania, Italy
Shashi Kumar , Jönköping University, Sweden
pp. iii-iv

Toward a science for future NoC design (Abstract)

R. Marculescu , Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 1-2

Router microarchitecture and scalability of ring topology in on-chip networks (Abstract)

J. Kim , Dept. of Comput. Sci., KAIST, Daejeon, South Korea
Hanjoon Kim , Dept. of Comput. Sci., KAIST, Daejeon, South Korea
pp. 5-10

Breaking adaptive multicast deadlock by virtual channel address/data FIFO decoupling (Abstract)

Ka-Ming Keung , Comput. Archit. Lab., Iowa State Univ., Ames, IA, USA
A. Tyagi , Comput. Archit. Lab., Iowa State Univ., Ames, IA, USA
pp. 11-16

Adaptive router architecture based on traffic behavior observability (Abstract)

D. Matos , PGMICRO, UFRGS - Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
C. Concatto , PGMICRO, UFRGS - Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
A. Kologeski , PGMICRO, UFRGS - Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
L. Carro , PGMICRO, UFRGS - Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
F. Kastensmidt , PGMICRO, UFRGS - Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
A. Susin , PGMICRO, UFRGS - Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
M. Kreutz , UFRN - Univ. of Rio Grande do Norte, Natal, Brazil
pp. 17-22

Architecture design principles for the integration of synchronization interfaces into network-on-chip switches (Abstract)

D. Ludovici , Comput. Eng. Lab., TUDelft, Delft, Netherlands
A. Strano , ENDIF, Univ. of Ferrara, Ferrara, Italy
D. Bertozzi , ENDIF, Univ. of Ferrara, Ferrara, Italy
pp. 31-36

Yield enhancement by robust application-specific mapping on network-on-chips (Abstract)

A. Dutta Choudhury , ALaRI, Univ. of Lugano, Lugano, Switzerland
G. Palermo , Dipt. di Elettron. e Inf., Politec. di Milano, Milan, Italy
C. Silvano , Dipt. di Elettron. e Inf., Politec. di Milano, Milan, Italy
V. Zaccaria , Dipt. di Elettron. e Inf., Politec. di Milano, Milan, Italy
pp. 37-42

The era of many-modules SoC: revisiting the NoC mapping problem (Abstract)

I. Walter , Dept. of Electr. Eng., Technion - Israel Inst. of Technol., Haifa, Israel
I. Cidon , Dept. of Electr. Eng., Technion - Israel Inst. of Technol., Haifa, Israel
A. Kolodny , Dept. of Electr. Eng., Technion - Israel Inst. of Technol., Haifa, Israel
D. Sigalov , Dept. of Appl. Math., Technion - Israel Inst. of Technol., Haifa, Israel
pp. 43-48

A performance evaluation of 2D-mesh, ring, and crossbar interconnects for chip multi-processors (Abstract)

J.C. Villanueva , Univ. Politec. de Valencia, Valencia, Spain
J. Flich , Univ. Politec. de Valencia, Valencia, Spain
J. Duato , Univ. Politec. de Valencia, Valencia, Spain
H. Eberle , Sun Microsyst., CA, USA
N. Gura , Sun Microsyst., CA, USA
W. Olesinski , Sun Microsyst., CA, USA
pp. 51-56

Segment gating for static energy reduction in networks-on-chip (Abstract)

K.C. Hale , Dept. of Comput. Sci., Univ. of Texas at Austin, Austin, TX, USA
B. Grot , Dept. of Comput. Sci., Univ. of Texas at Austin, Austin, TX, USA
S.W. Keckler , Dept. of Comput. Sci., Univ. of Texas at Austin, Austin, TX, USA
pp. 57-62

System-level exploration of run-time clusterization for energy-efficient on-chip communication (Abstract)

Liang Guang , Dept. of Inf. Technol., Univ. of Turku, Turku, Finland
E. Nigussie , Dept. of Inf. Technol., Univ. of Turku, Turku, Finland
H. Tenhunen , Dept. of Inf. Technol., Univ. of Turku, Turku, Finland
pp. 63-68

Hybrid wireless network on chip: A new paradigm in multi-core design (Abstract)

P.P. Pande , Sch. of EECS, Washington State Univ., Pullman, WA, USA
A. Ganguly , Sch. of EECS, Washington State Univ., Pullman, WA, USA
K. Chang , Sch. of EECS, Washington State Univ., Pullman, WA, USA
C. Teuscher , ECE Dept., Portland State Univ., Portland, OR, USA
pp. 71-76

Scalable arbitration of partitioned bus interconnection networks in 3D-IC systems (Abstract)

K. Ireland , Comput. Eng. Dept., Univ. of Pittsburgh, Pittsburgh, PA, USA
J. Jezak , Comput. Eng. Dept., Univ. of Pittsburgh, Pittsburgh, PA, USA
S. Levitan , Dept. of Electr. & Comput. Eng., Univ. of Pittsburgh, Pittsburgh, PA, USA
D. Chiarulli , Comput. Eng. Dept., Univ. of Pittsburgh, Pittsburgh, PA, USA
pp. 77-82

Wire cost and communication analysis of self-assembled interconnect models for networks-on-chip (Abstract)

C. Teuscher , ECE Dept., Portland State Univ., Portland, OR, USA
N. Parashar , ECE Dept., Portland State Univ., Portland, OR, USA
M. Mote , ECE Dept., Portland State Univ., Portland, OR, USA
N. Hergert , ECE Dept., Carnegie Mellon Univ., Pittsburgh, PA, USA
J. Aherne , ECE Dept., Portland State Univ., Portland, OR, USA
pp. 83-88
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