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2009 IEEE International Conference on Networking, Architecture, and Storage (2009)
Zhang Jia Jie, Hunan, China
July 9, 2009 to July 11, 2009
ISBN: 978-0-7695-3741-2
pp: 215-218
ABSTRACT
HyperTransport link is a high performance IO interface for system connection. In this paper, the architecture of a HyperTransport interface is introduced.This HyperTransport interface realizes efficient HT-AXI bidirectional transformation, where AXI is a popular bus protocol in SOC architectures. Furthermore, this HyperTransport interface provides dedicated hardware support for cache coherence protocol. Through this HyperTransport interface, Godson-3A multi-core processor chips can be interconnected together to forma 4-16 core CC-NUMA system or a large-scale NCCNUMA system. The verification of the HyperTransport interface is also presented.
INDEX TERMS
HyperTransport, Cache coherence, Interconnect
CITATION

D. Tang, H. Wang, Y. Chen and X. Gao, "An Enhanced HyperTransport Controller with Cache Coherence Support for Multiple-CMP," 2009 IEEE International Conference on Networking, Architecture, and Storage(NAS), Zhang Jia Jie, Hunan, China, 2009, pp. 215-218.
doi:10.1109/NAS.2009.46
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