2007 International Conference on Networking, Architecture, and Storage (NAS 2007) (2007)
July 29, 2007 to July 31, 2007
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/NAS.2007.54
Rong Ji , National University of Defense Technology, China
Xianjun Zeng , National University of Defense Technology, China
Liang Chen , National University of Defense Technology, China
Junfeng Zhang , National University of Defense Technology, China
The high clock frequency of current high-performan microprocessors brings the significant challenge for the microprocessors? power. The multiple clock domain (MCD) technique is a new clock distribution technique, which retains the benefits of synchronous designs and avoids the problems due to global clock to reduce the power of the clock distribution. Most present studies of MCD are only based on superscalar architectures. In this paper, a low-power clock distribution micro-architecture, named MCDE, the MCD microarchitecture based on explicitly parallel instruction computing (EPIC) is designed and implemented. Furthermore, a series of experiments on our design have been done to evaluate it. The experimental results show that, using a MCDE microarchitecture with a fine-grained dynamic frequency scaling algorithm, can effectively decrease the microprocessor power by 40%, compared with the conventional EPIC processor with only one clock domain.
X. Zeng, J. Zhang, L. Chen and R. Ji, "The Implementation and Design of a Low-Power Clock Distribution Microarchitecture," 2007 International Conference on Networking, Architecture, and Storage (NAS 2007)(NAS), Guilin, China, 2007, pp. 21-30.