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2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (2014)
Paris, France
July 8, 2014 to July 10, 2014
ISBN: 978-1-4799-6384-3
TABLE OF CONTENTS

[Front matter] (PDF)

pp. i-xiii

System-level assessment and area evaluation of Spin Wave logic circuits (Abstract)

Odysseas Zografos , IMEC, Leuven, Belgium
Praveen Raghavan , IMEC, Leuven, Belgium
Luca Amaru , Integrated Systems Laboratory, EPFL, Switzerland
Bart Soree , IMEC, Leuven, Belgium
Rudy Lauwereins , IMEC, Leuven, Belgium
Iuliana Radu , IMEC, Leuven, Belgium
Diederik Verkest , IMEC, Leuven, Belgium
Aaron Thean , IMEC, Leuven, Belgium
pp. 25-30

Memristor content addressable memory (Abstract)

Wanlong Chen , Future Computing Group School of Computing University of Kent Kent, UK
Xiao Yang , Future Computing Group School of Computing University of Kent Kent, UK
Frank Z. Wang , Future Computing Group School of Computing University of Kent Kent, UK
pp. 83-87

HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design (Abstract)

Pilin Junsangsri , Department of Electrical and Computer Engineering Northeastern University Boston, MA USA 02115
Fabrizio Lombardi , Department of Electrical and Computer Engineering Northeastern University Boston, MA USA 02115
Jie Han , Department of Electrical and Computer Engineering University of Alberta Edmonton, Canada
pp. 45-50

A memristor-based TCAM (Ternary Content Addressable Memory) cell (Abstract)

Pilin Junsangsri , Department of Electrical and Computer Engineering Northeastern University Boston, MA USA 02115
Fabrizio Lombardi , Department of Electrical and Computer Engineering Northeastern University Boston, MA USA 02115
Jie Han , Department of Electrical and Computer Engineering University of Alberta Edmonton, Canada
pp. 1-6

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection (Abstract)

Hassan Ghasemzadeh Mohammadi , Integrated Systems Laboratory, École Poly technique Federale deLausanne, Switzerland
Pierre-Emmanuel Gaillardon , Integrated Systems Laboratory, École Poly technique Federale deLausanne, Switzerland
Majid Yazdani , CLCL Laboratory (EPFL), University of Geneva, Switzerland
Giovanni De Micheli , Integrated Systems Laboratory, École Poly technique Federale deLausanne, Switzerland
pp. 163-168

A tunable cache for approximate computing (Abstract)

Magnus Sjalander , Uppsala University, Department of Information Technology P.O. Box 337, SE-751 05 Uppsala, Sweden
Nina Shariati Nilsson , Uppsala University, Department of Information Technology P.O. Box 337, SE-751 05 Uppsala, Sweden
Stefanos Kaxiras , Uppsala University, Department of Information Technology P.O. Box 337, SE-751 05 Uppsala, Sweden
pp. 88-89

NBTI aware IG-FinFET based SRAM design using adaptable trip-point sensing technique (Abstract)

Nandakishor Yadav , ABV-Indian Institute of Information Technology and Management Gwalior Gwalior (Madhya Pradesh), India - 474015
Shikha Jain , ABV-Indian Institute of Information Technology and Management Gwalior Gwalior (Madhya Pradesh), India - 474015
Manisha Pattanaik , ABV-Indian Institute of Information Technology and Management Gwalior Gwalior (Madhya Pradesh), India - 474015
G. K. Sharma , ABV-Indian Institute of Information Technology and Management Gwalior Gwalior (Madhya Pradesh), India - 474015
pp. 122-128

Compression architecture for bit-write reduction in non-volatile memory technologies (Abstract)

David B. Dgien , Department of Electrical and Computer Engineering, University of Pittsburgh, PA
Poovaiah M. Palangappa , Department of Electrical and Computer Engineering, University of Pittsburgh, PA
Nathan A. Hunter , Department of Electrical and Computer Engineering, University of Pittsburgh, PA
Jiayin Li , Department of Electrical and Computer Engineering, University of Pittsburgh, PA
Kartik Mohanram , Department of Electrical and Computer Engineering, University of Pittsburgh, PA
pp. 51-56

On-chip supervised learning rule for ultra high density neural crossbar using memristor for synapse and neuron (Abstract)

Djaafar Chabi , IEF, Univ Paris-Sud, Orsay, 91405, France
Zhaohao Wang , IEF, Univ Paris-Sud, Orsay, 91405, France
Weisheng Zhao , IEF, Univ Paris-Sud, Orsay, 91405, France
Jacques-Olivier Klein , IEF, Univ Paris-Sud, Orsay, 91405, France
pp. 7-12

Robust sequence storage in bistable oscillators (Abstract)

David Colliaux , ISIR, CNRS Université Pierre et Marie Curie, Paris
Pierre Bessiere , ISIR, CNRS Université Pierre et Marie Curie, Paris
Jacques Droulez , ISIR, CNRS Université Pierre et Marie Curie, Paris
pp. 90-91

Applications of wavelength-fan-in for high-performance distributed processing systems (Abstract)

Alexander N. Tait , Princeton University, Princeton, NJ, 08544 USA
Paul R. Prucnal , Princeton University, Princeton, NJ, 08544 USA
pp. 177-178

A CMOS-memristive self-learning neural network for pattern classification applications (Abstract)

Melika Payvand , University of California Santa Barbara Santa Barbara, CA, U.S.A
Justin Rofeh , University of California Santa Barbara Santa Barbara, CA, U.S.A
Avantika Sodhi , University of California Santa Barbara Santa Barbara, CA, U.S.A
Luke Theogarajan , University of California Santa Barbara Santa Barbara, CA, U.S.A
pp. 92-97

Floating-point unit design with nano-electro-mechanical (NEM) relays (Abstract)

Sumit Dutta , Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge, MA 02139
Vladimir Stojanovic , Department of Electrical Engineering and Computer Sciences University of California Berkeley, CA 94720
pp. 145-150

Sub-crosspoint RRAM decoding for improved area efficiency (Abstract)

Ravi Patel , Department of Electrical and Computer Engineering University of Rochester Rochester, New York 14627
Eby G. Friedman , Department of Electrical and Computer Engineering University of Rochester Rochester, New York 14627
pp. 98-103

Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires (Abstract)

N. Ben-Romdhane , IEF, Univ. Paris-Sud, Orsay, 91405, France
W. S. Zhao , IEF, Univ. Paris-Sud, Orsay, 91405, France
Y. Zhang , IEF, Univ. Paris-Sud, Orsay, 91405, France
J-O. Klein , IEF, Univ. Paris-Sud, Orsay, 91405, France
Z. R. Wang , IEF, Univ. Paris-Sud, Orsay, 91405, France
D. Ravelosona , IEF, Univ. Paris-Sud, Orsay, 91405, France
pp. 71-76

Analog-to-stochastic converter using magnetic-tunnel junction devices (Abstract)

Naoya Onizawa , Frontier Research Institute for Interdisciplinary Sciences, Tohoku University, Sendai, Miyagi, Japan 980-8578
Daisaku Katagiri , Research Institute of Tohoku University, Sendai, Miyagi, Japan 980-8577
Warren J. Gross , Department of Electrical and Computer Engineering, McGill University, Montreal, Canada H3A 0E9
Takahiro Hanyu , Research Institute of Tohoku University, Sendai, Miyagi, Japan 980-8577
pp. 59-64

A standard cell approach for MagnetoElastic NML circuits (Abstract)

D. Giri , Politecnico di Torino, Department of Electronics and Telecommunications, Corso Duca degli Abruzzi, 24, 10129 Torino, Italy
M. Vacca , Politecnico di Torino, Department of Electronics and Telecommunications, Corso Duca degli Abruzzi, 24, 10129 Torino, Italy
G. Causapruno , Politecnico di Torino, Department of Electronics and Telecommunications, Corso Duca degli Abruzzi, 24, 10129 Torino, Italy
Wenjing Rao , University of Illinois at Chicago, Electrical and Computer Engineering Department, 851 S. Morgan St, Chicago (IL)
M. Graziano , Politecnico di Torino, Department of Electronics and Telecommunications, Corso Duca degli Abruzzi, 24, 10129 Torino, Italy
M. Zamboni , Politecnico di Torino, Department of Electronics and Telecommunications, Corso Duca degli Abruzzi, 24, 10129 Torino, Italy
pp. 65-70

Molecular transistor circuits: From device model to circuit simulation (Abstract)

A. Zahir , Department of Electronics and Telecommunications, Politecnico di Torino, Italy
S. A. A. Zaidi , Department of Electronics and Telecommunications, Politecnico di Torino, Italy
A. Pulimeno , Department of Electronics and Telecommunications, Politecnico di Torino, Italy
M. Graziano , Department of Electronics and Telecommunications, Politecnico di Torino, Italy
D. Demarchi , Department of Electronics and Telecommunications, Politecnico di Torino, Italy
G. Masera , Department of Electronics and Telecommunications, Politecnico di Torino, Italy
G. Piccinini , Department of Electronics and Telecommunications, Politecnico di Torino, Italy
pp. 129-134

Volatile memristive devices as short-term memory in a neuromorphic learning architecture (Abstract)

Jens Burger , Department of Electrical and Computer Engineering Portland State University, Portland, OR, USA
Christof Teuscher , Department of Electrical and Computer Engineering Portland State University, Portland, OR, USA
pp. 104-109

Wave-based multi-valued computation framework (Abstract)

Santosh Khasanvis , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, MA, USA
Mostafizur Rahman , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, MA, USA
Sankara Narayanan Rajapandian , Nvidia Corporation, CA, USA
Csaba Andras Moritz , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, MA, USA
pp. 171-176

STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing (Abstract)

Kejie Huang , Singapore University of Technology and Design 20 Dover Road, Singapore, 138682
Rong Zhao , Singapore University of Technology and Design 20 Dover Road, Singapore, 138682
Yong Lian , Lassonde School of Engineering York University, Canada, M4P 2A7
pp. 31-36

Pipeline design in spintronic circuits (Abstract)

Nickvash Kani , School of Electrical and Computer Engineering, Georgia Institute of Technology, 791 Atlantic Dr., Atlanta, GA 30332, USA
Azad Naeemi , School of Electrical and Computer Engineering, Georgia Institute of Technology, 791 Atlantic Dr., Atlanta, GA 30332, USA
pp. 110-115

Monte Carlo simulations of carbon nanotube networks for optoelectronic applications (Abstract)

Miguel Diez-Garcia , Institut d'Electronique Fondamentale, Univ. Paris-Sud, CNRS 91405 Orsay, France
Adrien F. Vincent , Institut d'Electronique Fondamentale, Univ. Paris-Sud, CNRS 91405 Orsay, France
Nicolas Izard , Institut d'Electronique Fondamentale, Univ. Paris-Sud, CNRS 91405 Orsay, France
Damien Querlioz , Institut d'Electronique Fondamentale, Univ. Paris-Sud, CNRS 91405 Orsay, France
pp. 135-136

Integration of threshold logic gates with RRAM devices for energy efficient and robust operation (Abstract)

Jinghua Yang , School of Computing, Informatics and Decision Systems Engineering Arizona State University, Tempe, Arizona, 85281
Niranjan Kulkarni , School of Computing, Informatics and Decision Systems Engineering Arizona State University, Tempe, Arizona, 85281
Shimeng Yu , School of Computing, Informatics and Decision Systems Engineering Arizona State University, Tempe, Arizona, 85281
Sarma Vrudhula , School of Computing, Informatics and Decision Systems Engineering Arizona State University, Tempe, Arizona, 85281
pp. 39-44

Sneak paths effects in CBRAM memristive devices arrays for spiking neural networks (Abstract)

David Roclin , CEA, LIST, Laboratory For Enhancing Reliability of Embedded systems, F-91191 Gif-sur-Yvette, France
Olivier Bichler , CEA, LIST, Laboratory For Enhancing Reliability of Embedded systems, F-91191 Gif-sur-Yvette, France
Christian Gamrat , CEA, LIST, Laboratory For Enhancing Reliability of Embedded systems, F-91191 Gif-sur-Yvette, France
Jacques-Olivier Klein , IEF, Univ Paris-Sud, UMR 8622, Orsay, F-91405
pp. 13-18

A low contact resistance graphene field effect transistor with single-layer-channel and multi-layer-contact (Abstract)

Honghui Sun , State Key Laboratory of High Performance Computing National University of Defense Technology Changsha, 410073, P.R. China
Liang Fang , State Key Laboratory of High Performance Computing National University of Defense Technology Changsha, 410073, P.R. China
Yao Wang , School of Computer National University of Defense Technology Changsha, 410073, P.R. China
Yaqing Chi , School of Computer National University of Defense Technology Changsha, 410073, P.R. China
Rulin Liu , State Key Laboratory of High Performance Computing National University of Defense Technology Changsha, 410073, P.R. China
pp. 139-144

On the influence of synaptic weight states in a locally competitive algorithm for memristive hardware (Abstract)

Walt Woods , Department of Electrical and Computer Engineering Portland State University, Portland, OR, USA
Jens Burger , Department of Electrical and Computer Engineering Portland State University, Portland, OR, USA
Christof Teuscher , Department of Electrical and Computer Engineering Portland State University, Portland, OR, USA
pp. 19-24

A model for variation- and fault-tolerant digital logic using self-assembled nanowire architectures (Abstract)

Alireza Goudarzi , Department of Computer Science University of New Mexico Albuquerque, NM 87131, USA
Matthew R. Lakin , Department of Computer Science University of New Mexico Albuquerque, NM 87131, USA
Darko Stefanovic , Department of Computer Science University of New Mexico Albuquerque, NM 87131, USA
Christof Teuscher , Department of Electrical and Computer Engineering Portland State University Portland, OR 97201, USA
pp. 116-121

A new Tunnel-FET based RAM concept for ultra-low power applications (Abstract)

Mostafizur Rahman , Electrical & Computer Engineering Department, University of Massachusetts Amherst, MA 01003, USA
Mingyu Li , Electrical & Computer Engineering Department, University of Massachusetts Amherst, MA 01003, USA
Jiajun Shi , Electrical & Computer Engineering Department, University of Massachusetts Amherst, MA 01003, USA
Santosh Khasanvis , Electrical & Computer Engineering Department, University of Massachusetts Amherst, MA 01003, USA
C. Andras Moritz , Electrical & Computer Engineering Department, University of Massachusetts Amherst, MA 01003, USA
pp. 57-58

Energy effective 3D stacked hybrid NEMFET-CMOS caches (Abstract)

Mihai Lefter , Faculty of EEMCS, Delft University of Technology, The Netherlands
Marius Enachescu , Faculty of EEMCS, Delft University of Technology, The Netherlands
George Razvan Voicu , Faculty of EEMCS, Delft University of Technology, The Netherlands
Sorin Dan Cotofana , Faculty of EEMCS, Delft University of Technology, The Netherlands
pp. 151-156

Stochastic reliability evaluation of Sea-of-Tiles based on Double Gate controllable-polarity FETs (Abstract)

Catherine Dezan , Lab-STICC, CNRS UMR 6285, Université de Bretagne Occidendale, Brest, France
Sara Zermani , Lab-STICC, CNRS UMR 6285, Université de Bretagne Occidendale, Brest, France
pp. 169-170

Spin torque nano oscillators as key building blocks for the Systems-on-Chip of the future (Abstract)

Mircea R. Stan , ECE Department, University of Virginia Charlottesville, VA, USA
Mehdi Kabir , ECE Department, University of Virginia Charlottesville, VA, USA
Stu Wolf , MSE Department, University of Virginia Charlottesville, VA, USA
Jiwei Lu , MSE Department, University of Virginia Charlottesville, VA, USA
pp. 37-38

Virtual prototyping of R2D NASIC based FPGA (Abstract)

Ciprian Teodorov , UMR 6285 Lab-STICC ENSTA Bretagne Brest, France
Loic Lagadec , UMR 6285 Lab-STICC ENSTA Bretagne Brest, France
pp. 179-180
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