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2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 2012) (2012)
Amsterdam
July 4, 2012 to July 6, 2012
ISSN: 2327-8218
ISBN: 978-1-4503-1671-2
TABLE OF CONTENTS

[Front matter] (PDF)

pp. i-xi

Ambipolar circuits for analog, mixed-signal, and radio-frequency applications (PDF)

Kartik Mohanram , Department of Electrical and Computer Engineering, University of Pittsburgh, USA
Xuebei Yang , Department of Electrical and Computer Engineering, Rice University, USA
Guanxiong Liu , Department of Electrical and Computer Engineering, University of California, Riverside, USA
Masoud Rostami , Department of Electrical and Computer Engineering, Rice University, USA
Alexander Balandin , Department of Electrical and Computer Engineering, University of California, Riverside, USA
pp. 1-6

Ambipolar double gate CNTFETs based reconfigurable Logic cells (PDF)

Kotb Jabeur , Lyon Institute of Nanotechnology - Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
Ian O'Connor , Lyon Institute of Nanotechnology - Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
Sebastien Le Beux , Lyon Institute of Nanotechnology - Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
David Navarro , Lyon Institute of Nanotechnology - Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
pp. 7-13

Low-power design technique with ambipolar double gate devices (PDF)

Kotb Jabeur , Lyon Institute of Nanotechnology - Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
Ian O'Connor , Lyon Institute of Nanotechnology - Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
David Navarro , Lyon Institute of Nanotechnology - Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
Sebastien Le Beux , Lyon Institute of Nanotechnology - Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
pp. 14-21

Gate-level modeling for CMOS circuit simulation with ultimate FinFETs (PDF)

Nicolas Chevillon , InESS / Université de Strasbourg, Parc d'innovation, BP 10413, 67412 Illkirch Cedex, France
Morgan Madec , InESS / Université de Strasbourg, Parc d'innovation, BP 10413, 67412 Illkirch Cedex, France
Christophe Lallement , InESS / Université de Strasbourg, Parc d'innovation, BP 10413, 67412 Illkirch Cedex, France
pp. 22-29

Design exploration of ultra-low power non-volatile memory based on topological insulator (PDF)

Yuhao Wang , School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798
Hao Yu , School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore 639798
pp. 30-35

A conventional design for CLB implementation of a FPGA in Quantum-dot Cellular Automata (QCA) (PDF)

Moein Kianpour , Electrical Engineering Department, Islamic Azad University, Central Tehran Branch, Iran
Reza Sabbaghi-Nadooshan , Electrical Engineering Department, Islamic Azad University, Central Tehran Branch, Iran
pp. 36-42

Introducing OVP awareness to achieve an efficient permanent defect locating (PDF)

Tanvir Ahmed , Computing Architecture Lab., Nara Institute of Science and Technology(NAIST), Takayama-Cho 8916-5, Ikoma 630-0192, Japan
Jun Yao , Computing Architecture Lab., Nara Institute of Science and Technology(NAIST), Takayama-Cho 8916-5, Ikoma 630-0192, Japan
Yasuhiko Nakashima , Computing Architecture Lab., Nara Institute of Science and Technology(NAIST), Takayama-Cho 8916-5, Ikoma 630-0192, Japan
pp. 43-49

Irreversibility induced density limits and logical reversiblity in nanocircuits (PDF)

Ismo Hanninen , Department of Computer Systems, Tampere University of Technology, Finland
Jarmo Takala , Department of Computer Systems, Tampere University of Technology, Finland
pp. 50-54

Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors (PDF)

Shashikanth Bobba , LSI, EPFL, Lausanne, Switzerland
Pierre-Emmanuel Gaillardon , LSI, EPFL, Lausanne, Switzerland
Jian Zhang , LSI, EPFL, Lausanne, Switzerland
Michele De Marchi , LSI, EPFL, Lausanne, Switzerland
Davide Sacchetto , LSM, EPFL, Lausanne, Switzerland
Yusuf Leblebici , LSM, EPFL, Lausanne, Switzerland
Giovanni De Micheli , LSI, EPFL, Lausanne, Switzerland
pp. 55-60

Ambipolar independent double gate FET logic (PDF)

Ian O'Connor , Lyon Institute of Nanotechnology - Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
Kotb Jabeur , Lyon Institute of Nanotechnology - Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
Sebastien Le Beux , Lyon Institute of Nanotechnology - Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
David Navarro , Lyon Institute of Nanotechnology - Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
pp. 61-68

Ternary volatile random access memory based on heterogeneous graphene-CMOS fabric (PDF)

Santosh Khasanvis , University of Massachusetts at Amherst, USA
K. M. Masum Habib , University of California Riverside, USA
Mostafizur Rahman , University of Massachusetts at Amherst, USA
Pritish Narayanan , University of Massachusetts at Amherst, USA
Roger K. Lake , University of California Riverside, USA
Csaba Andras Moritz , University of Massachusetts at Amherst, USA
pp. 69-76

Macromodeling a phase change memory (PCM) cell by HSPICE (PDF)

Pilin Junsangsri , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA USA 02115
Fabrizio Lombardi , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA USA 02115
Jie Han , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada
pp. 77-84

Crossbar architecture based on 2R complementary resistive switching memory cell (PDF)

W.S. Zhao , IEF, Univ. Paris-Sud, - UMR8622, CNRS, Orsay, France
Y. Zhang , IEF, Univ. Paris-Sud, - UMR8622, CNRS, Orsay, France
J.O Klein , IEF, Univ. Paris-Sud, - UMR8622, CNRS, Orsay, France
D. Querlioz , IEF, Univ. Paris-Sud, - UMR8622, CNRS, Orsay, France
D. Chabi , IEF, Univ. Paris-Sud, - UMR8622, CNRS, Orsay, France
D. Ravelosona , IEF, Univ. Paris-Sud, - UMR8622, CNRS, Orsay, France
C. Chappert , IEF, Univ. Paris-Sud, - UMR8622, CNRS, Orsay, France
J.M. Portal , Aix-Marseille University, IM2NP - UMR CNRS 7334, France
M. Bocquet , Aix-Marseille University, IM2NP - UMR CNRS 7334, France
H. Aziza , Aix-Marseille University, IM2NP - UMR CNRS 7334, France
D. Deleruyelle , Aix-Marseille University, IM2NP - UMR CNRS 7334, France
C. Muller , Aix-Marseille University, IM2NP - UMR CNRS 7334, France
pp. 85-92

A Monte Carlo analysis of a write method used in passive nanoelectronic crossbars (PDF)

Arne Heittmann , Electrical Engineering and Computer Systems, RWTH Aachen University, D-52062, Germany
Tobias G. Noll , Electrical Engineering and Computer Systems, RWTH Aachen University, D-52062, Germany
pp. 93-100

RRAM-based FPGA for “normally off, instantly on” applications (PDF)

O. Turkyilmaz , LETI, CEA, Grenoble, France
S. Onkaraiah , LETI, CEA, Grenoble, France
M. Reyboz , LETI, CEA, Grenoble, France
F. Clermidy , LETI, CEA, Grenoble, France
Costin Anghel Hraziia , ISEP, Paris, France
J. Portal , Aix-Marseille Univ., Marseille, France
Marc Bocquet , Aix-Marseille Univ., Marseille, France
pp. 101-108

Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices (PDF)

Yao Wang , Computer Engineering Laboratory, EEMCS, Delft University of Technology, 2628CD, the Netherlands
Sorin D. Cotofana , Computer Engineering Laboratory, EEMCS, Delft University of Technology, 2628CD, the Netherlands
Liang Fang , School of Computer Science, National University of Defense Technology, Changsha, 410073, China
pp. 109-115

A Markovian, variation-aware circuit-level aging model (PDF)

Nicoleta Cucu Laurenciu , Computer Engineering Laboratory, Delft University of Technology, The Netherlands
Sorin Dan Cotofana , Computer Engineering Laboratory, Delft University of Technology, The Netherlands
pp. 116-122

Zero-performance-overhead online fault detection and diagnosis in 3D stacked integrated circuits (PDF)

Saleh Safiruddin , Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, The Netherlands
Mihai Lefter , Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, The Netherlands
Demid Borodin , Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, The Netherlands
George Voicu , Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, The Netherlands
Sorin Dan Cotofana , Faculty of Electrical Engineering, Mathematics and Computer Science, Delft University of Technology, The Netherlands
pp. 123-130

Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs (PDF)

Jinghang Liang , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada
Linbin Chen , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA
Jie Han , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada
Fabrizio Lombardi , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA
pp. 131-138

Emitter-coupled spin-transistor logic (PDF)

Joseph S. Friedman , Department of Electrical Engineering & Computer Science, Northwestern University, Evanston, IL USA
Yehea I. Ismail , Department of Electrical Engineering & Computer Science, Northwestern University, Evanston, IL USA
Gokhan Memik , Department of Electrical Engineering & Computer Science, Northwestern University, Evanston, IL USA
Alan V. Sahakian , Department of Electrical Engineering & Computer Science, Northwestern University, Evanston, IL USA
Bruce W. Wessels , Department of Electrical Engineering & Computer Science, Northwestern University, Evanston, IL USA
pp. 139-145

Room temperature double gate Single Electron Transistor based standard cell library (PDF)

Mohamed Amine Bounouar , 3IT-CRN2, Dept. of Electrical and Computer Engineering, Université de Sherbrooke, QC, Canada
Arnaud Beaumont , Lyon Institute of Nanotechnology, Université de Lyon, INSA-Lyon, F-69621 Villeurbanne Cedex, France
Khalil El Hajjam , Lyon Institute of Nanotechnology, Université de Lyon, INSA-Lyon, F-69621 Villeurbanne Cedex, France
Francis Calmon , Lyon Institute of Nanotechnology, Université de Lyon, INSA-Lyon, F-69621 Villeurbanne Cedex, France
Dominique Drouin , 3IT-CRN2, Dept. of Electrical and Computer Engineering, Université de Sherbrooke, QC, Canada
pp. 146-151

Cell design and comparative evaluation of a novel 1T memristor-based memory (PDF)

Vikas Sakode , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA USA 02115
Fabrizio Lombardi , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA USA 02115
Jie Han , Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Canada
pp. 152-159

ToPoliNano: Nanoarchitectures design made real (PDF)

S. Frache , Electronics and Telecommunications Department, Politecnico di Torino, c.so Duca degli Abruzzi 24, Italy
D. Chiabrando , Electronics and Telecommunications Department, Politecnico di Torino, c.so Duca degli Abruzzi 24, Italy
M. Graziano , Electronics and Telecommunications Department, Politecnico di Torino, c.so Duca degli Abruzzi 24, Italy
F. Riente , Electronics and Telecommunications Department, Politecnico di Torino, c.so Duca degli Abruzzi 24, Italy
G. Turvani , Electronics and Telecommunications Department, Politecnico di Torino, c.so Duca degli Abruzzi 24, Italy
M. Zamboni , Electronics and Telecommunications Department, Politecnico di Torino, c.so Duca degli Abruzzi 24, Italy
pp. 160-167

A novel write-scheme for data integrity in memristor-based crossbar memories (PDF)

Angelo Giuseppe Ruotolo , University of Rome “Tor Vergata”, ITALY
Marco Ottavi , University of Rome “Tor Vergata”, ITALY
Salvatore Pontarelli , University of Rome “Tor Vergata”, ITALY
Fabrizio Lombardi , Northeastern University, Boston MA, USA
pp. 168-173

Stigmergic search with Single Electron Tunneling technology based Memory Enhanced Hubs (PDF)

Saleh Safiruddin , Faculty of EE, Mathematics and CS, Delft University of Technology, The Netherlands
Sorin Cotofana , Faculty of EE, Mathematics and CS, Delft University of Technology, The Netherlands
Ferdinand Peper , Brain ICT Laboratory, National Institute of Information and Communications Technology, Kobe, Japan
pp. 174-180

Synthesis of topological quantum circuits (PDF)

Alexandru Paler , Faculty of Informatics and Mathematics, University of Passau, Innstr. 43, D-94032, Germany
Simon Devitt , National Institute of Informatics, 2-1-2 Hitotsubashi, Chiyoda-ku, Tokyo, Japan
Kae Nemoto , National Institute of Informatics, 2-1-2 Hitotsubashi, Chiyoda-ku, Tokyo, Japan
Ilia Polian , Faculty of Informatics and Mathematics, University of Passau, Innstr. 43, D-94032, Germany
pp. 181-187

Spintronic Threshold Logic Array (STLA) - a compact, low leakage, non-volatile gate array architecture (PDF)

Nishant S. Nukala , School of Computing, Informatics and Decision Systems Engineering, Arizona State University, Tempe, 85281, U.S.A.
Niranjan Kulkarni , School of Computing, Informatics and Decision Systems Engineering, Arizona State University, Tempe, 85281, U.S.A.
Sarma Vrudhula , School of Computing, Informatics and Decision Systems Engineering, Arizona State University, Tempe, 85281, U.S.A.
pp. 188-195

Spin wave nanofabric update (PDF)

J. G. Alzate , Electrical Engineering Department, University of California - Los Angeles, USA
P. Upadhyaya , Electrical Engineering Department, University of California - Los Angeles, USA
M. Lewis , Electrical Engineering Department, University of California - Los Angeles, USA
J. Nath , Electrical Engineering Department, University of California - Los Angeles, USA
Y. T. Lin , Electrical Engineering Department, University of California - Los Angeles, USA
K. Wong , Electrical Engineering Department, University of California - Los Angeles, USA
S. Cherepov , Electrical Engineering Department, University of California - Los Angeles, USA
P. Khalili Amiri , Electrical Engineering Department, University of California - Los Angeles, USA
K.L. Wang , Electrical Engineering Department, University of California - Los Angeles, USA
J. Hockel , Mechanical and Aerospace Engineering Department, University of California - Los Angeles, USA
A. Bur , Mechanical and Aerospace Engineering Department, University of California - Los Angeles, USA
G. P. Carman , Mechanical and Aerospace Engineering Department, University of California - Los Angeles, USA
S. Bender , Department of Physics and Astronomy, University of California - Los Angeles, USA
Y. Tserkovnyak , Department of Physics and Astronomy, University of California - Los Angeles, USA
J. Zhu , Department of Physics and Astronomy, University of California - Irvine, USA
Y-J Chen , Department of Physics and Astronomy, University of California - Irvine, USA
I. N. Krivorotov , Department of Physics and Astronomy, University of California - Irvine, USA
J. Katine , Hitachi GST Research Center, San Jose, USA
J. Langer , Singulus Technologies AG, Kahl am Main, Germany
P. Shabadi , Electrical and Computer Engineering Department, University of Massachusetts in Amherst, USA
S. Khasanvis , Electrical and Computer Engineering Department, University of Massachusetts in Amherst, USA
S. Narayanan , Electrical and Computer Engineering Department, University of Massachusetts in Amherst, USA
C. A. Moritz , Electrical and Computer Engineering Department, University of Massachusetts in Amherst, USA
A. Khitun , Electrical Engineering Department, University of California - Riverside, USA
pp. 196-202

Bioinspired networks with nanoscale memristive devices that combine the unsupervised and supervised learning approaches (PDF)

D. Querlioz , institut d'Electronique Fondamentale, Univ. Paris-Sud, CNRS, Orsay, France
W. S. Zhao , institut d'Electronique Fondamentale, Univ. Paris-Sud, CNRS, Orsay, France
P. Dollfus , institut d'Electronique Fondamentale, Univ. Paris-Sud, CNRS, Orsay, France
J.-O. Klein , institut d'Electronique Fondamentale, Univ. Paris-Sud, CNRS, Orsay, France
O. Bichler , CEA, LIST, Embedded Computing Laboratory, Gif-Sur-Yvette, France
C. Gamrat , CEA, LIST, Embedded Computing Laboratory, Gif-Sur-Yvette, France
pp. 203-210

Ultra low energy analog image processing using spin based neurons (PDF)

Mrigank Sharad , Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA
Charles Augustine , Circuit Research Lab, Intel labs, Intel Corporation, Hillsboro, OR, US
Georgios Panagopoulos , Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA
Kaushik Roy , Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA
pp. 211-217

RRAM-based adaptive neural logic block for implementing non-linearly separable functions in a single layer (PDF)

Michael Soltiz , NanoComputing Research Group, Department of Computer Engineering, Rochester Institute of Technology, NY 14623, USA
Cory Merkel , NanoComputing Research Group, Department of Computer Engineering, Rochester Institute of Technology, NY 14623, USA
Dhireesha Kudithipudi , NanoComputing Research Group, Department of Computer Engineering, Rochester Institute of Technology, NY 14623, USA
Garrett S. Rose , Information Directorate, Air Force Research Laboratory, Rome, NY 13441, USA
pp. 218-225

Memristor-based reservoir computing (PDF)

Manjari S. Kulkarni , Department of Electrical and Computer Engineering, Portland State University, OR USA
Christof Teuscher , Department of Electrical and Computer Engineering, Portland State University, OR USA
pp. 226-232
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