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2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (2011)
San Diego, CA, USA
June 8, 2011 to June 9, 2011
ISBN: 978-1-4577-0993-7
TABLE OF CONTENTS
Papers

[Title page] (Abstract)

pp. i-vi

mrFPGA: A novel FPGA architecture with memristor-based reconfiguration (Abstract)

Jason Cong , Department of Computer Science, University of California, Los Angeles, USA
Bingjun Xiao , Department of Computer Science, University of California, Los Angeles, USA
pp. 1-8

Ultra-fine grain FPGAs: A granularity study (Abstract)

M. Haykel Ben-Jamaa , CEA, LETI, MINATEC Campus, Grenoble, France
Fabien Clermidy , CEA, LETI, MINATEC Campus, Grenoble, France
Pierre-Emmanuel Gaillardon , CEA, LETI, MINATEC Campus, Grenoble, France
Ian O'Connor , Université de Lyon, France
pp. 9-15

A hybrid memory cell using Single-Electron transfer (Abstract)

Jie Han , Dept of ECE, University of Alberta, Edmonton, Canada
Wei Wei , Department of ECE, Northeastern University, Boston, MA 02115, USA
Fabrizio Lombardi , Department of ECE, Northeastern University, Boston, MA 02115, USA
pp. 16-23

Inexact computing for ultra low-power nanometer digital circuit design (Abstract)

Jaeyoon Kim , School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, USA
Sandip Tiwari , School of Electrical and Computer Engineering, Cornell University, Ithaca, NY, USA
pp. 24-31

Scalability and design-space analysis of a 1T-1MTJ memory cell (Abstract)

Richard Dorrance , Department of Electrical Engineering, University of California, Los Angeles, USA
Dejan Markovic , Department of Electrical Engineering, University of California, Los Angeles, USA
Amr Amin , Department of Electrical Engineering, University of California, Los Angeles, USA
Yuta Toriyama , Department of Electrical Engineering, University of California, Los Angeles, USA
Fengbo Ren , Department of Electrical Engineering, University of California, Los Angeles, USA
C.-K. Ken Yang , Department of Electrical Engineering, University of California, Los Angeles, USA
pp. 32-36

Improving performance of NEM relay logic circuits using integrated charge-boosting flip flop (Abstract)

Poras T. Balsara , VLSI Circuits and Systems Laboratory, University of Texas at Dallas, Richardson 75080, USA
Ramakrishnan Venkatasubramanian , VLSI Circuits and Systems Laboratory, University of Texas at Dallas, Richardson 75080, USA
Sujan K. Manohar , VLSI Circuits and Systems Laboratory, University of Texas at Dallas, Richardson 75080, USA
pp. 37-44

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design (Abstract)

Vijaykrishnan Narayanan , Department of Computer Science and Engineering, Pennsylvania State University, University Park, 16802, USA
Suman Datta , Department of Electrical Engineering, Pennsylvania State University, University Park, 16802, USA
Jaydeep P. Kulkarni , Circuit Research Lab, Intel Corporation, Hillsboro, OR 97124-5961, USA
Vinay Saripalli , Department of Computer Science and Engineering, Pennsylvania State University, University Park, 16802, USA
pp. 45-52

Analysis of STT-RAM cell design with multiple MTJs per access (Abstract)

C.K. Ken Yang , Department of Electrical Engineering, University of California, Los Angeles, 90095, USA
Dejan Markovic , Department of Electrical Engineering, University of California, Los Angeles, 90095, USA
Fengbo Ren , Department of Electrical Engineering, University of California, Los Angeles, 90095, USA
Henry Park , Department of Electrical Engineering, University of California, Los Angeles, 90095, USA
Amr Amin , Department of Electrical Engineering, University of California, Los Angeles, 90095, USA
Richard Dorrance , Department of Electrical Engineering, University of California, Los Angeles, 90095, USA
pp. 53-58

3D-HIM: A 3D High-density Interleaved Memory for bipolar RRAM design (Abstract)

Yi-Chung Chen , Dept. of ECE, Polytechnic Institute of NYU, Brooklyn, USA
Hai Li , Dept. of ECE, Polytechnic Institute of NYU, Brooklyn, USA
Wei Zhang , School of Computer Engineering, Nanyang Technological University, Singapore
Robinson E. Pino , Advanced Computing, Air Force Research Laboratory, Rome, NY, USA
pp. 59-64

Using OxRRAM memories for improving communications of reconfigurable FPGA architectures (Abstract)

Fabien Clermidy , CEA-LETI, MINATEC Campus, Grenoble, France
Christophe Muller , IM2NP, UMR CNRS 6242, Aix-Marseille Université, France
Marina Reyboz , CEA-LETI, MINATEC Campus, Grenoble, France
Pierre-Emmanuel Gaillardon , CEA-LETI, MINATEC Campus, Grenoble, France
Marc Bocquet , IM2NP, UMR CNRS 6242, Aix-Marseille Université, France
Jean-Michel Portal , IM2NP, UMR CNRS 6242, Aix-Marseille Université, France
Santhosh Onkaraiah , CEA-LETI, MINATEC Campus, Grenoble, France
pp. 65-69

Regular 2D NASIC-based architecture and design space exploration (Abstract)

Catherine Dezan , Lab-STICC CNRS UMR 3192, Université de Bretagne Occidentale, Brest, France
Loic Lagadec , Lab-STICC CNRS UMR 3192, Université de Bretagne Occidentale, Brest, France
Ciprian Teodorov , Lab-STICC CNRS UMR 3192, Université de Bretagne Occidentale, Brest, France
Pritish Narayanan , Nanoscale Computing Fabrics Laboratory, University of Massachusetts, Amherst, USA
pp. 70-77
Papers

Graphene nanoribbon crossbar nanomesh (Abstract)

K. M. M. Habib , Department of Electrical Engineering, University of California Riverside, 92506 U.S.A.
A. A. Balandin , Department of Electrical Engineering, University of California Riverside, 92506 U.S.A.
R. K. Lake , Department of Electrical Engineering, University of California Riverside, 92506 U.S.A.
A. Khitun , Department of Electrical Engineering, University of California Riverside, 92506 U.S.A.
pp. 86-90

Nanofabric power analysis: Biosequence alignment case study (Abstract)

Luca Gaetano Amaru , Electronics Department, Politecnico di Torino, c.so Duca degli Abruzzi 24, Italy
Maurizio Zamboni , Electronics Department, Politecnico di Torino, c.so Duca degli Abruzzi 24, Italy
Mariagrazia Graziano , Electronics Department, Politecnico di Torino, c.so Duca degli Abruzzi 24, Italy
Stefano Frache , Electronics Department, Politecnico di Torino, c.so Duca degli Abruzzi 24, Italy
pp. 91-98

Nanoscale Application Specific Integrated Circuits (Abstract)

Michael Leuchtenburg , University of Massachusetts Amherst, USA
Mostafizur Rahman , University of Massachusetts Amherst, USA
Csaba Andras Moritz , University of Massachusetts Amherst, USA
Priyamvada Vijayakumar , University of Massachusetts Amherst, USA
Pritish Narayanan , University of Massachusetts Amherst, USA
Pavan Panchapakeshan , University of Massachusetts Amherst, USA
Israel Koren , University of Massachusetts Amherst, USA
Jorge Kina , University of California Los Angeles, USA
Kyeong-Sik Shin , University of California Los Angeles, USA
Chi On Chui , University of California Los Angeles, USA
pp. 99-106

Spin wave functions nanofabric update (Abstract)

C. Andras Moritz , University of Massachusetts at Amherst, 01003 USA
Alexander Khitun , University of California Riverside, 92521 USA
Kin Wong , University of California Los Angeles, 90024 USA
P. Khalili Amiri , University of California Los Angeles, 90024 USA
Prasad Shabadi , University of Massachusetts at Amherst, 01003 USA
Kang L. Wang , University of California Los Angeles, 90024 USA
pp. 107-113

Power efficient nanophotonic on-chip network for future large scale multiprocessor architectures (Abstract)

Somayyeh Koohi , Computer Engineering Department, Sharif University of Technology, Tehran, Iran
Shaahin Hessabi , Computer Engineering Department, Sharif University of Technology, Tehran, Iran
pp. 114-121

Energy efficient many-core processor for recognition and mining using spin-based memory (Abstract)

Charles Augustine , School of Electrical and Computer Engineering, Purdue University, USA
Vinay K. Chippa , School of Electrical and Computer Engineering, Purdue University, USA
Rangharajan Venkatesan , School of Electrical and Computer Engineering, Purdue University, USA
Kaushik Roy , School of Electrical and Computer Engineering, Purdue University, USA
Anand Raghunathan , School of Electrical and Computer Engineering, Purdue University, USA
pp. 122-128

Low-power functionality enhanced computation architecture using spin-based devices (Abstract)

Srikant Srinivasan , Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN - 47907, USA
Behtash Behin-Aein , Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN - 47907, USA
Kaushik Roy , Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN - 47907, USA
Angik Sarkar , Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN - 47907, USA
Georgios Panagopoulos , Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN - 47907, USA
Charles Augustine , Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN - 47907, USA
pp. 129-136

Robust neural logic block (NLB) based on memristor crossbar array (Abstract)

Weisheng Zhao , IEF, Univ. Paris-Sud 11, Orsay, France
Damien Querlioz , IEF, Univ. Paris-Sud 11, Orsay, France
Djaafar Chabi , IEF, Univ. Paris-Sud 11, Orsay, France
Jacques-Olivier Klein , IEF, Univ. Paris-Sud 11, Orsay, France
pp. 137-143

A scheme for computation in nanoscale dynamical systems: Gated discrete phase-shift interactions (Abstract)

Paul M. Riechers , Department of Electrical and Computer Engineering, University of California at Davis, USA
Richard A. Kiehl , Department of Electrical and Computer Engineering, University of California at Davis, USA
pp. 144-149

Learning with memristive devices: How should we model their behavior? (Abstract)

Olivier Bichler , CEA, LIST, Embedded Computers Laboratory, Gif-Sur-Yvette, France
Christian Gamrat , CEA, LIST, Embedded Computers Laboratory, Gif-Sur-Yvette, France
Damien Querlioz , Institut d'Electronique Fondamentale, Univ. Paris-Sud, CNRS, Orsay, France
Philippe Dollfus , Institut d'Electronique Fondamentale, Univ. Paris-Sud, CNRS, Orsay, France
pp. 150-156

Performance assessment of partially unzipped carbon nanotube field-effect transistors (Abstract)

Sayeef Salahuddin , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, 94720, USA
Youngki Yoon , Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, 94720, USA
pp. 157-161

Ambipolar double-gate FET binary-decision- diagram (Am-BDD) for reconfigurable logic cells (Abstract)

I. O'Connor , Lyon Institute of Nanotechnology, University of Lyon, Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
S. Le Beux , Lyon Institute of Nanotechnology, University of Lyon, Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
N. Yakymets , Lyon Institute of Nanotechnology, University of Lyon, Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
K. Jabeur , Lyon Institute of Nanotechnology, University of Lyon, Ecole Centrale de Lyon, 36 avenue Guy de Collongue, F-69134 Ecully, France
pp. 162-168

Determining fundamental heat dissipation bounds for transistor-based nanocomputing paradigms (Abstract)

Mostafizur Rahman , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, 01003-9292, USA
Ilke Ercan , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, 01003-9292, USA
Neal G. Anderson , Department of Electrical and Computer Engineering, University of Massachusetts Amherst, 01003-9292, USA
pp. 169-174

A unified aging model of NBTI and HCI degradation towards lifetime reliability management for nanoscale MOSFET circuits (Abstract)

Yao Wang , Computer Engineering Laboratory, EEMCS, Delft University of Technology, 2628CD, the Netherlands
Sorin Cotofana , Computer Engineering Laboratory, EEMCS, Delft University of Technology, 2628CD, the Netherlands
Liang Fang , School of Computer Science, National University of Defense Technology, Changsha, 410073, China
pp. 175-180

Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics (Abstract)

Priyamvada Vijayakumar , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Israel Koren , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Pritish Narayanan , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Csaba Andras Moritz , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
C. Mani Krishna , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
pp. 181-188

Hybrid Graphene Nanoribbon-CMOS tunneling volatile memory fabric (Abstract)

K. M. Masum Habib , University of California Riverside, 92521-0204 USA
Roger K. Lake , University of California Riverside, 92521-0204 USA
Csaba Andras Moritz , University of Massachusetts at Amherst, 01003 USA
Pritish Narayanan , University of Massachusetts at Amherst, 01003 USA
Mostafizur Rahman , University of Massachusetts at Amherst, 01003 USA
Santosh Khasanvis , University of Massachusetts at Amherst, 01003 USA
pp. 189-195

N<sup>3</sup>ASICs: Designing nanofabrics with fine-grained CMOS integration (Abstract)

Pavan Panchapakeshan , Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Pritish Narayanan , Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Csaba Andras Moritz , Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
pp. 196-202

Towards "zero-energy" using NEMFET-based power management for 3D hybrid stacked ICs (Abstract)

Sorin Dan Cotofana , Faculty of EE, Mathematics and CS, Delft University of Technology, The Netherlands
George Razvan Voicu , Faculty of EE, Mathematics and CS, Delft University of Technology, The Netherlands
Marius Enachescu , Faculty of EE, Mathematics and CS, Delft University of Technology, The Netherlands
pp. 203-209

NEMTronics: Symbiotic integration of nanoelectronic and nanomechanical devices for energy-efficient adaptive computing (Abstract)

Seetharam Narasimhan , Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, Ohio, USA
Somnath Paul , Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, Ohio, USA
Xinmu Wang , Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, Ohio, USA
Swarup Bhunia , Department of Electrical Engineering and Computer Science, Case Western Reserve University, Cleveland, Ohio, USA
pp. 210-217

NEMS based thermal management for 3D many-core system (Abstract)

Xiwei Huang , School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
Wei Zhang , School of Computer Engineering, Nanyang Technological University, Singapore
Hao Yu , School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
pp. 218-223
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