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2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (2010)
Anaheim, CA, USA
June 17, 2010 to June 18, 2010
ISBN: 978-1-4244-8020-3
TABLE OF CONTENTS
Papers

Front matter (Abstract)

pp. i-ix

[Front matter] (PDF)

pp. i-ix
Papers

Memristor based programmable threshold logic array (Abstract)

Jeyavijayan Rajendran , Department of Electrical and Computer Engineering Polytechnic Institute of New York University, Brooklyn, NY - 11201
Harika Manem , Department of Electrical and Computer Engineering Polytechnic Institute of New York University, Brooklyn, NY - 11201
Ramesh Karri , Department of Electrical and Computer Engineering Polytechnic Institute of New York University, Brooklyn, NY - 11201
Garrett S. Rose , Department of Electrical and Computer Engineering Polytechnic Institute of New York University, Brooklyn, NY - 11201
pp. 5-10

Towards logic functions as the device (Abstract)

Kang L. Wang , University of California Los Angeles, Los Angeles, CA 90024 USA
C. Andras Moritz , University of Massachusetts at Amherst, Amherst, MA 01003 USA
Prasad Shabadi , University of Massachusetts at Amherst, Amherst, MA 01003 USA
Pritish Narayanan , University of Massachusetts at Amherst, Amherst, MA 01003 USA
Israel Koren , University of Massachusetts at Amherst, Amherst, MA 01003 USA
Mingqiang Bao , University of California Los Angeles, Los Angeles, CA 90024 USA
Alexander Khitun , University of California Los Angeles, Los Angeles, CA 90024 USA
pp. 11-16

High throughput and low power dissipation in QCA pipelines using Bennett clocking (Abstract)

Adelio Salsano , University of Rome “Tor Vergata” Italy
Erik DeBenedictis , Sandia National Laboratories, Albuquerque NM
Peter Kogge , University of Notre Dame, South Bend IN
Fabrizio Lombardi , Northeastern University, Boston MA
Salvatore Pontarelli , University of Rome “Tor Vergata” Italy
Marco Ottavi , University of Rome “Tor Vergata” Italy
pp. 17-22

Fast equivalence-checking for quantum circuits (Abstract)

Igor L. Markov , University of Michigan, 2260 Hayward St., Ann Arbor, Michigan 48109, U.S.A.
Shigeru Yamashita , Ritsumeikan University, 1-1-1 Noji Higashi, Kusatsu, Shiga 525-8577, Japan
pp. 23-28

Design and comparison of NML systolic architectures (Abstract)

Michael Niemier , Department of Computer Science and Engineering, University of Notre Dame Notre Dame, IN 46556, USA
X. Sharon Hu , Department of Computer Science and Engineering, University of Notre Dame Notre Dame, IN 46556, USA
Michael Crocker , Department of Computer Science and Engineering, University of Notre Dame Notre Dame, IN 46556, USA
pp. 29-34

UNION: A unified inter/intra-chip optical network for chip multiprocessors (Abstract)

Xuan Wang , Department of Electrical and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong, PRC
Jiang Xu , Department of Electrical and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong, PRC
Xiaowen Wu , Department of Electrical and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong, PRC
Yaoyao Ye , Department of Electrical and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong, PRC
Wei Zhang , School of Computer Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore
Weichen Liu , Department of Electrical and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong, PRC
Mahdi Nikdast , Department of Electrical and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong, PRC
pp. 35-40

Fault modeling for FinFET circuits (Abstract)

Ajay Bhoj , Department of Electrical Engineering, Princeton University, Princeton, NJ 08544
Muzaffer O. Simsir , Department of Electrical Engineering, Princeton University, Princeton, NJ 08544
Niraj K. Jha , Department of Electrical Engineering, Princeton University, Princeton, NJ 08544
pp. 41-46

Reducing transistor count in clocked standard cells with ambipolar double-gate FETs (Abstract)

I. O'Connor , Lyon Institute of Nanotechnology, University of Lyon, Ecole Centrale de Lyon, Ecully, France
D. Navarro , Lyon Institute of Nanotechnology, University of Lyon, Ecole Centrale de Lyon, Ecully, France
F. Clermidy , CEA-LETI-MINATEC, Grenoble, France
P. E. Gaillardon , CEA-LETI-MINATEC, Grenoble, France
K. Jabeur , Lyon Institute of Nanotechnology, University of Lyon, Ecole Centrale de Lyon, Ecully, France
M. H. Ben Jamaa , CEA-LETI-MINATEC, Grenoble, France
pp. 47-52

NanoV: Nanowire-based VLSI design (Abstract)

Niraj K. Jha , Department of Electrical Engineering, Princeton University, Princeton, NJ 08544
Muzaffer O. Simsir , Department of Electrical Engineering, Princeton University, Princeton, NJ 08544
pp. 53-58

Stochastic nanoscale addressing for logic (Abstract)

Eric Rachlin , Department of Computer Science, Brown University
John E. Savage , Department of Computer Science, Brown University
pp. 59-64

Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications (Abstract)

M. Haykel Ben Jamaa , CEA-LETI-MINATEC, 17, Rue des Martyrs, F-38054 Grenoble, France
Giovanni De Micheli , EPFL, Lausanne, Switzerland
Michele De Marchi , EPFL, Lausanne, Switzerland
pp. 65-70

Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes (Abstract)

Rehman Ashraf , Department of Electrical and Computer Engineering, Portland State University, Portland, OR, USA
Malgorzata Chrzanowska-Jeske , Department of Electrical and Computer Engineering, Portland State University, Portland, OR, USA
Siva G. Narendra , Department of Electrical and Computer Engineering, Portland State University, Portland, OR, USA
Rajeev K. Nain , Department of Electrical and Computer Engineering, Portland State University, Portland, OR, USA
pp. 71-76

Intel LVS logic as a combinational logic paradigm in CNT technology (Abstract)

Pushan Tang , EE Department, Fudan University, Shanghai, China, 200433
Jun Tao , EE Department, Fudan University, Shanghai, China, 200433
Zhen Cao , EE Department, Fudan University, Shanghai, China, 200433
Xuan Zeng , EE Department, Fudan University, Shanghai, China, 200433
Philip H.-S. Wong , Stanford University, Stanford, CA, 94305-4075
Bao Liu , ECE Department, The University of Texas, San Antonio, TX, 78249-0669
pp. 77-81
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