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2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (2009)
San Francisco, CA, USA
July 30, 2009 to July 31, 2009
ISBN: 978-1-4244-4957-6
TABLE OF CONTENTS
Papers

Computing with nanoscale memory: Model and architecture (Abstract)

Somnath Paul , Department of Electrical Engineering and Computer Science Case Western Reserve University, Cleveland, OH-44106, USA
Swarup Bhunia , Department of Electrical Engineering and Computer Science Case Western Reserve University, Cleveland, OH-44106, USA
pp. 1-6

Compact modeling and corner analysis of spintronic memristor (Abstract)

Yiran Chen , Seagate Technology, 1280 Disc Dr., Shakopee, MN 55379, USA
Xiaobin Wang , Seagate Technology, 7801 Computer Ave, Bloomington, MN 55435, USA
pp. 7-12

Challenges in scalable fault tolerance (Abstract)

Patrick Lincoln , Computer Science Laboratory, SRI International, Menlo Park, CA 94025, USA
pp. 13-14

A coding framework for DNA self-assembly (Abstract)

Zahra Mashreghian Arani , Northeastern University, Dept. of ECE, Boston MA 02115, USA
Masoud Hashempour , Northeastern University, Dept. of ECE, Boston MA 02115, USA
Fabrizio Lombardi , Northeastern University, Dept. of ECE, Boston MA 02115, USA
pp. 15-20

System-level energy and performance projections for nanomagnet-based logic (Abstract)

Michael Garrison , Department of Computer Science and Engineering, USA
X. Sharon Hu , Department of Computer Science and Engineering, USA
M. Tanvir Alam , Department of Electrical Engineering, University of Notre Dame, IN 46556, USA
Michael Niemier , Department of Computer Science and Engineering, USA
Aaron Dingler , Department of Computer Science and Engineering, USA
pp. 21-26

Residue-based code for reliable hybrid memories (Abstract)

Said Hamdioui , Computer Engineering Laboratory, Delft University of Technology, The Netherlands
Nor Zaidi Haron , Computer Engineering Laboratory, Delft University of Technology, The Netherlands
pp. 27-32

Stateful implication logic with memristors (Abstract)

Mika Laiho , University of Turku, Department of Information Technology, FI-20014, Finland
Eero Lehtonen , University of Turku, Department of Information Technology, FI-20014, Finland
pp. 33-36

Validating cascading of crossbar circuits with an integrated device-circuit exploration (Abstract)

Chi On Chui , Department of Electrical Engineering, University of California, Los Angeles, USA
Pritish Narayanan , Electrical&Computer Engineering, University of Massachusetts Amherst, USA
Kyoung Won Park , Department of Electrical Engineering, University of California, Los Angeles, USA
Csaba Andras Moritz , Electrical&Computer Engineering, University of Massachusetts Amherst, USA
pp. 37-42

Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism (Abstract)

Aissa Melouki , School of Electronics and Computer Science, University of Southampton, UK
Bashir M. Al-Hashimi , School of Electronics and Computer Science, University of Southampton, UK
Saket Srivastava , School of Electronics and Computer Science, University of Southampton, UK
pp. 43-46

Design of a Goldschmidt iterative divider for quantum-dot cellular automata (Abstract)

Inwook Kong , Department of Electrical and Computer Engineering, University of Texas at Austin, 78712, USA
Seong-Wan Kim , Department of Electrical and Computer Engineering, University of Texas at Austin, 78712, USA
Earl E. Swartzlander , Department of Electrical and Computer Engineering, University of Texas at Austin, 78712, USA
pp. 47-50

Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network (Abstract)

Soumya Eachempati , Dept. of Computer Science and Engineering, Pennsylvania State University, University Park, USA
Aditya Yanamandra , Dept. of Computer Science and Engineering, Pennsylvania State University, University Park, USA
Vijaykrishnan Narayanan , Dept. of Computer Science and Engineering, Pennsylvania State University, University Park, USA
Mary Jane Irwin , Dept. of Computer Science and Engineering, Pennsylvania State University, University Park, USA
Yuan Xie , Dept. of Computer Science and Engineering, Pennsylvania State University, University Park, USA
pp. 51-56

Using carbon nanotube in digital memories (Abstract)

Tong Zhang , Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180 USA
Shu Li , Department of Electrical, Computer and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY 12180 USA
pp. 57-60

FPGA based on integration of carbon nanorelays and CMOS devices (Abstract)

Ming Liu , Institute of Electronics, Chinese Academy of Sciences, Beijing, China
Wei Wang , College of Nanoscales Science and Engineering, University at Albany, State University of New York, USA
Haigang Yang , Institute of Electronics, Chinese Academy of Sciences, Beijing, China
Sansiri Tanachutiwat , College of Nanoscales Science and Engineering, University at Albany, State University of New York, USA
pp. 61-64

Adaptive Clock Scheduling for pipelined structures (Abstract)

Sorin Cotofana , Computer Engineering Lab, Delft University of Technology, The Netherlands
Ben Kuiper , Computer Engineering Lab, Delft University of Technology, The Netherlands
pp. 65-68

Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices (Abstract)

Junchen Liu , Ecole Centrale de Lyon, 36, avenue Guy de Collongue, F-69134 Ecully, France
Pierre-Emmanuel Gaillardon , CEA-LETI-MINATEC, 17, rue des Martyrs, F-38054 Grenoble, France
Fabien Clermidy , CEA-LETI-MINATEC, 17, rue des Martyrs, F-38054 Grenoble, France
Ian O'Connor , Ecole Centrale de Lyon, 36, avenue Guy de Collongue, F-69134 Ecully, France
pp. 69-74

Runtime analysis for defect-tolerant logic mapping on nanoscale crossbar architectures (Abstract)

Yehua Su , ECE Department, University of Illinois at Chicago, 60607, USA
Wenjing Rao , ECE Department, University of Illinois at Chicago, 60607, USA
pp. 75-78

Online detection of multiple faults in crossbar nano-architectures using dual rail implementations (Abstract)

Mehdi B. Tahoori , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA
Navid Farazmand , Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA
pp. 79-82
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