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2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (2008)
Anaheim, CA, USA
June 12, 2008 to June 13, 2008
ISBN: 978-1-4244-2552-5
TABLE OF CONTENTS
Papers

System level performance analysis of carbon nanotube global interconnects for emerging chip multiprocessors (Abstract)

Nikil Dutt , Center for Embedded Computer Systems, University of California at Irvine, 92697, USA
Fadi Kurdahi , Center for Embedded Computer Systems, University of California at Irvine, 92697, USA
Sudeep Pasricha , Center for Embedded Computer Systems, University of California at Irvine, 92697, USA
pp. 1-7

Online test and fault-tolerance for nanoelectronic programmable logic arrays (Abstract)

Alex Orailoglu , Department of Computer Science and Engineering, University of California, San Diego 9500 Gilman Drive, La Jolla, 92037, USA
Saturnino Garcia , Department of Computer Science and Engineering, University of California, San Diego 9500 Gilman Drive, La Jolla, 92037, USA
pp. 8-15

Assessing random dynamical network architectures for nanoelectronics (Abstract)

Thimo Rohlf , Max Planck Institute for Mathematics in the Sciences, Leipzig, Germany
Christof Teuscher , Computer, Computational&Statistical Sciences Division, Los Alamos National Laboratory, USA
Natali Gulbahce , Center for Complex Networks Research, Northeastern University, USA
pp. 16-23

Locality aware redundancy allocation in nanoelectronic systems (Abstract)

Alex Orailoglu , UC San Diego, CSE Department, USA
Wenjing Rao , U of Illinois at Chicago, ECE Department, USA
Keith Marzullo , UC San Diego, CSE Department, USA
pp. 24-31

A DSP nanosystem with defect tolerance (Abstract)

Weiguo Tang , Department of Electrical and Computer Engineering, University of Connecticut, Storrs, 06269, USA
Lei Wang , Department of Electrical and Computer Engineering, University of Connecticut, Storrs, 06269, USA
pp. 32-37

A voterless strategy for defect-tolerant nano-architectures (Abstract)

M. Nourami , Center for Integrated Circuits&Systems, The University of Texas at Dallas, Richardson, 75083, USA
A. Namazi , Center for Integrated Circuits&Systems, The University of Texas at Dallas, Richardson, 75083, USA
M. Saquib , Center for Integrated Circuits&Systems, The University of Texas at Dallas, Richardson, 75083, USA
pp. 38-45

Defect tolerance in QCA-based PLAs (Abstract)

X. Sharon Hu , Department of Computer Science and Engineering, University of Notre Dame, IN 46556, USA
Michael Crocker , Department of Computer Science and Engineering, University of Notre Dame, IN 46556, USA
Michael Niemier , Department of Computer Science and Engineering, University of Notre Dame, IN 46556, USA
pp. 46-53

On brain-inspired connectivity and hybrid network topologies (Abstract)

Peter M. Kelly , School of Intelligent Systems, University of Ulster (UU), Magee Campus, Londonderry, United Kingdom
Valeriu Beiu , Department of Computer System Engineering (CSE), College of IT (CIT), UAE University (UAEU), Al Ain, United Arab Emirates
Liam J. McDaid , School of Intelligent Systems, University of Ulster (UU), Magee Campus, Londonderry, United Kingdom
Basheer A. M. Madappuram , Department of Computer System Engineering (CSE), College of IT (CIT), UAE University (UAEU), Al Ain, United Arab Emirates
pp. 54-61

Reconfigurable BDD based quantum circuits (Abstract)

N. Vijaykrishnan , Dept. of Computer Science and Engineering, Pennsylvania State University, University Park, USA
Suman Datta , Dept. of Electrical Engineering, Pennsylvania State University, University Park, USA
Soumya Eachempati , Dept. of Computer Science and Engineering, Pennsylvania State University, University Park, USA
Vinay Saripalli , Dept. of Computer Science and Engineering, Pennsylvania State University, University Park, USA
pp. 61-67

Single Electron Tunneling Delay Insensitive and fluctuation based computation paradigms and circuits (Abstract)

Saleh Safiruddin , Computer Engineering Laboratory, Delft University of Technology, The Netherlands
Sorin Dan Cotofana , Computer Engineering Laboratory, Delft University of Technology, The Netherlands
Ferdinand Peper , Nano ICT Group - National Institute of Information and Communications Technology, Kobe, Japan
pp. 69-76

Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis (Abstract)

Anish Muttreja , Dept. of Electrical Engineering, Princeton University, NJ 08544, USA
Niraj K. Jha , Dept. of Electrical Engineering, Princeton University, NJ 08544, USA
Prateek Mishra , Dept. of Electrical Engineering, Princeton University, NJ 08544, USA
pp. 77-84

Spike-timing-dependent learning in memristive nanodevices (Abstract)

Greg S. Snider , Information and Quantum Systems Laboratory, Hewlett-Packard Laboratories, Palo Alto, CA USA
pp. 85-92

rFGA: CMOS-nano hybrid FPGA using RRAM components (Abstract)

Wei Wang , College of Nanoscale Science and Engineering, State University of New York at Albany, USA
Ming Liu , Lab of Nano-fabrication and Novel Devices Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
pp. 93-98
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