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2008 IEEE International Symposium on Nanoscale Architectures (2008)
Anaheim, CA, USA
June 12, 2008 to June 13, 2008
ISBN: 978-1-4244-2552-5
pp: 93-98
Ming Liu , Lab of Nano-fabrication and Novel Devices Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
Wei Wang , College of Nanoscale Science and Engineering, State University of New York at Albany, USA
In this paper, novel reconfigurable architectures are introduced to utilize high-density resistive memory (RRAM) to build FPGA components. Different from the existing CMOS-nano hybrid circuits that use crossbars, the proposed rFPGA structures consist of mainly 1T1R structures (1 CMOS transistor is integrated with a two-terminal resistive nanojunction) that can be fabricated using a CMOS-compatible process. The proposed 2D architecture maintains the baseline FPGA cell designs and significantly reduces the size of memory and routing elements using 1T1R structures. The proposed 3D architecture further improves the density of the 2D version by efficiently integrating RRAM and CMOS layers in three dimensions. The simulation results demonstrate that the proposed 2D and 3D FPGA structures can provide at least 2X–3X performance gains, compared to the corresponding 2D and 3D CMOS FPGA’s.

Wei Wang and Ming Liu, "rFGA: CMOS-nano hybrid FPGA using RRAM components," 2008 IEEE International Symposium on Nanoscale Architectures(NANOARCH), Anaheim, CA, USA, 2008, pp. 93-98.
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