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2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) (2007)
San Jose, CA, USA
Oct. 21, 2007 to Oct. 22, 2007
ISBN: 978-1-4244-1790-2
TABLE OF CONTENTS
Papers

Dynamic redundancy allocation for reliable and high-performance nanocomputing (Abstract)

Shuo Wang , Department of Electrical and Computer Engineering, University of Connecticut, USA
Lei Wang , Department of Electrical and Computer Engineering, University of Connecticut, USA
Faquir Jain , Department of Electrical and Computer Engineering, University of Connecticut, USA
pp. 1-6

Design-space exploration of fault-tolerant building blocks for large-scale quantum computing (Abstract)

Isaac L. Chuang , Massachussetts Institute of Technology, Cambridge, 02139, USA
Andrew W. Cross , Massachussetts Institute of Technology, Cambridge, 02139, USA
Darshan D. Thaker , University of California at Davis, 95616, USA
Tzvetan S. Metodi , University of California at Davis, 95616, USA
Frederic T. Chong , University of California at Santa Barbara, 93106, USA
pp. 7-14

A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions (Abstract)

Michael Orshansky , Department of Electrical and Computer Engineering, University of Texas at Austin, USA
Adnan Aziz , Department of Electrical and Computer Engineering, University of Texas at Austin, USA
Ashish Singh , Department of Electrical and Computer Engineering, University of Texas at Austin, USA
Hady Ali Zeineddine , Department of Electrical and Computer Engineering, University of Texas at Austin, USA
Sriram Vishwanath , Department of Electrical and Computer Engineering, University of Texas at Austin, USA
pp. 15-20

Analysis of defect tolerance in molecular electronics using information-theoretic measures (Abstract)

Jianwei Dai , Department of Electrical and Computer Engineering, University of Connecticut, 371 Fairfield Road, U-2157, Storrs, 06269, USA
Faquir Jain , Department of Electrical and Computer Engineering, University of Connecticut, 371 Fairfield Road, U-2157, Storrs, 06269, USA
Lei Wang , Department of Electrical and Computer Engineering, University of Connecticut, 371 Fairfield Road, U-2157, Storrs, 06269, USA
pp. 21-26

Design automation for hybrid CMOS-nonoelectronics crossbars (Abstract)

Ramesh Karri , Dept, of Electrical&Computer Engineering, Polytechnic University, Brooklyn, NY, USA
Alex Orailoglu , Dept. of Computer Science&Engineering, University of California, San Diego, La Jolla, USA
Kyosun Kim , Dept. of Electronic Engineering, University of Incheon, Korea
pp. 27-32

A fast, numerical circuit-level model of carbon nanotube transistor (Abstract)

Bashir M. Al-Hashimi , School of Electronics and Computer Science, University of Southampton, SO17 1BJ, UK
Tom J. Kazmierski , School of Electronics and Computer Science, University of Southampton, SO17 1BJ, UK
Dafeng Zhou , School of Electronics and Computer Science, University of Southampton, SO17 1BJ, UK
pp. 33-37

A ballistic nanoelectronic device simulator (Abstract)

Dennis Huo , Department of Electrical and Computer Engineering, University of Rochester, New York, 14627, USA
Paul Ampadu , Department of Electrical and Computer Engineering, University of Rochester, New York, 14627, USA
Qiaoyan Yu , Department of Electrical and Computer Engineering, University of Rochester, New York, 14627, USA
pp. 38-45

Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations (Abstract)

Drew C. Ness , University of Minnesota, Department of Scientific Computation, EECS building, 200 Union St SE, Minneapolis, 55455-0167, USA
David J. Lilja , University of Minnesota, Department of Scientific Computation, EECS building, 200 Union St SE, Minneapolis, 55455-0167, USA
Christian J. Hescott , University of Minnesota, Department of Electrical and Computer Engineering, EECS building, 200 Union St SE, Minneapolis, 55455-0167, USA
pp. 46-53

A shift-register-based QCA memory architecture (Abstract)

Dan Venutolo , Department of Electrical and Computer Engineering, Drexel University, Philadelphia, 19104, USA
Andy Chiu , Department of Electrical and Computer Engineering, Drexel University, Philadelphia, 19104, USA
Jonathan Salkind , Department of Electrical and Computer Engineering, Drexel University, Philadelphia, 19104, USA
Baris Taskin , Department of Electrical and Computer Engineering, Drexel University, Philadelphia, 19104, USA
pp. 54-61

Thermally-induced soft errors in nanoscale CMOS circuits (Abstract)

H. Li , Division of Engineering, Brown University, Providence, RI 02912, USA
D. Kazazis , Division of Engineering, Brown University, Providence, RI 02912, USA
W. Patterson , Division of Engineering, Brown University, Providence, RI 02912, USA
R. I. Bahar , Division of Engineering, Brown University, Providence, RI 02912, USA
A. Zaslavsky , Division of Engineering, Brown University, Providence, RI 02912, USA
J. Mundy , Division of Engineering, Brown University, Providence, RI 02912, USA
pp. 62-69

Robust self-assembly of interconnects by parallel DNA growth (Abstract)

Masoud Hashempour , Northeastern University, Dept. of ECE, Boston, MA, 02115, USA
Zahra Mashreghian Arani , Northeastern University, Dept. of ECE, Boston, MA, 02115, USA
Fabrizio Lombardi , Northeastern University, Dept. of ECE, Boston, MA, 02115, USA
pp. 70-76

Design of high-yield defect-tolerant self-assembled nanoscale memories (Abstract)

P. Oscar Boykin , Advanced Computing and Information Systems Laboratory, University of Florida, 32611, USA
Renato J. Figueiredo , Advanced Computing and Information Systems Laboratory, University of Florida, 32611, USA
Girish Venkatasubramanian , Advanced Computing and Information Systems Laboratory, University of Florida, 32611, USA
pp. 77-84

A pageable, defect-tolerant nanoscale memory system (Abstract)

Tzvetan S. Metodi , University of California, Santa Barbara, USA
Susmit Biswas , University of California, Santa Barbara, USA
Ryan Kastner , University of California, Santa Barbara, USA
Frederic T. Chong , University of California, Santa Barbara, USA
pp. 85-92

Emerging nanocircuit paradigm: Graphene-based electronics for nanoscale computing (Abstract)

Q. W. Shi , Hefei National Laboratory for Physical Sciences at Microscale, Canada
Z. F. Wang , Hefei National Laboratory for Physical Sciences at Microscale, Canada
Huaixiu Zheng , Electrical and Computer Engineering, University of Alberta, T6G 2V4, Canada
Jie Chen , Electrical and Computer Engineering, University of Alberta, T6G 2V4, Canada
pp. 93-100

Combining 2-level logic families in grid-based nanoscale fabrics (Abstract)

Csaba Andras Moritz , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Pritish Narayanan , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
Teng Wang , Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, USA
pp. 101-108

Prospects for the development of digital CMOL circuits (Abstract)

Konstantin K. Likharev , Stony Brook University, NY 11794-3800, U.S.A
Dmitri B. Strukov , Hewlett-Packard Laboratories, Palo Alto, CA 94304-1126, U.S.A.
pp. 109-116

Crossbar latch-based combinational and sequential logic for nano FPGA (Abstract)

W. Badawy , ECE Dept., University of Calgary, T2N1N4, Canada
T. Mohamed , ECE Dept., University of Calgary, T2N1N4, Canada
G. A. Jullien , ECE Dept., University of Calgary, T2N1N4, Canada
pp. 117-122

Clocking nanocircuits for nanocomputers and other nanoelectronic systems (Abstract)

Shamik Das , Nanosystems Group, The MITRE Corporation, 7515 Colshire Dr., McLean, VA 22102, USA
Matthew F. Bauwens , Nanosystems Group, The MITRE Corporation, 7515 Colshire Dr., McLean, VA 22102, USA
pp. 123-128
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