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Multimedia and Ubiquitous Engineering, International Conference on (2007)
Seoul, Korea
Apr. 26, 2007 to Apr. 28, 2007
ISBN: 0-7695-2777-9
pp: 220-225
Jong-Wha Chong , Hanyang University, Korea
Kyeong-Yuk Min , Hanyang University, Korea
In this paper, we propose memory and performance optimized architecture to accelerate the operation speed of adaptive deblocking filter for H.264/JVT/AVC video coding. The proposed deblocking filter executes loading/storing and filtering operations with only 232 cycles for 1 macroblock. Only 2x4x4 internal buffers and 32x16 internal SRAM are adopted for the buffering operation of deblocking filter with I/O bandwidth of 32 bit. The proposed architecture can process the filtering operation for 1 macroblock with less filtering cycles and lower memory sizes than some conventional approaches of realizing deblocking filter. The efficient hardware architecture is implemented with novel data arrangement, hybrid filter scheduling and minimum number of buffer. The proposed architecture is suitable for low cost and real-time applications, and the real-time decoding with 1080HD(1920x1088@30fps) can be easily achieved when working frequency is 85.2MHz.
Jong-Wha Chong, Kyeong-Yuk Min, "A Memory and Performance Optimized Architecture of Deblocking Filter in H.264/AVC", Multimedia and Ubiquitous Engineering, International Conference on, vol. 00, no. , pp. 220-225, 2007, doi:10.1109/MUE.2007.21
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