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Fifth International Workshop on Microprocessor Test and Verification (MTV'04) (2005)
Austin, Texas
Nov. 3, 2005 to Nov. 5, 2005
ISSN: 1550-4093
ISBN: 0-7695-2627-6
TABLE OF CONTENTS
Introduction

Preface (PDF)

pp. vii

Acknowledgement (PDF)

pp. viii
Architecture Description Languages

A Study of Architecture Description Languages from a Model-based Perspective (Abstract)

Sharad Malik , Princeton University, USA
Wei Qin , Boston University, USA
pp. 3-11

An Introduction to the Plasma Language (Abstract)

Peter Wilson , Freescale Semiconductor Inc, USA
Aseem Gupta , University of California, Irvine, USA
Brian Kahne , Freescale Semiconductor Inc, USA
Nikil Dutt , University of California, Irvine, USA
pp. 12-22
SAT Applications

On SAT-based Bounded Invariant Checking of Blackbox Designs (Abstract)

Bernd Becker , Albert-Ludwigs-University, Germany
Marc Herbstritt , Albert-Ludwigs-University, Germany
pp. 23-28

PaMira - A Parallel SAT Solver with Knowledge Sharing (Abstract)

Tobias Schubert , Albert-Ludwigs-University of Freiburg, Germany
Bernd Becker , Albert-Ludwigs-University of Freiburg, Germany
Matthew Lewis , Albert-Ludwigs-University of Freiburg, Germany
pp. 29-36
Debug and Diagnosis

Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets (Abstract)

E. Sanchez , Politecnico di Torino, Italy
P. Bernardi , Politecnico di Torino, Italy
M. Schillaci , Politecnico di Torino, Italy
G. Squillero , Politecnico di Torino, Italy
M. Sonza Reorda , Politecnico di Torino, Italy
pp. 37-41

Post-Verification Debugging of Hierarchical Designs (Abstract)

Moayad Fahim Ali , University of Toronto, Canada
Rolf Drechsler , University of Bremen, Germany
Magdy S. Abadir , Freescale Semiconductor, USA
Sean Safarpour , University of Toronto, Canada
Andreas Veneris , University of Toronto, Canada
pp. 42-47

Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores (Abstract)

M. Sonza Reorda , Politecnico di Torino, Italy
P. Bernardi , Politecnico di Torino, Italy
M. Rebaudengo , Politecnico di Torino, Italy
M. Grosso , Politecnico di Torino, Italy
pp. 55-62
High Level Test and ATPG

Is IDDQ Test of Microprocessors Feasible? (Abstract)

D. M. H. Walker , Texas A&M University, USA
Bin Xue , Intel Corp., USA
pp. 63-69

A Pseudo-Deterministic Functional ATPG based on EFSM Traversing (Abstract)

F. Fummi , Universita di Verona, Italy
G. Di Guglielmo , Universita di Verona, Italy
G. Pravadelli , Universita di Verona, Italy
C. Marconcini , Universita di Verona, Italy
pp. 70-75

Simulation Data Mining for Functional Test Pattern Justification (Abstract)

Li-C. Wang , University of California, Santa Barbara, USA
Charles H.-P. Wen , University of California, Santa Barbara, USA
pp. 76-83

Search-Space Optimizations for High-Level ATPG (Abstract)

Hussain Al-Asaad , University of California, Davis, USA
Jorge Campos , University of California, Davis, USA
pp. 84-89

A TDM Test Scheduling Method for Network-on-Chip Systems (Abstract)

John Mark Nolen , Texas A&M University, USA
Rabi Mahapatra , Texas A&M University, USA
pp. 90-98
Validation

Automated Extraction of Structural Information from SystemC-based IP for Validation (Abstract)

Hiren D. Patel , Virginia Polytechnic and State University, USA
David Berner , Institut de Recherche en Informatique et Systemes Aleatoires (IRISA/INRIA), France
Sandeep K. Shukla , Virginia Polytechnic and State University, USA
Deepak A. Mathaikutty , Virginia Polytechnic and State University, USA
pp. 99-104

Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors (Abstract)

Jayanta Bhadra , Freescale Semiconductor Inc., USA
David Burgess , Freescale Semiconductor Inc., USA
Magdy S. Abadir , Freescale Semiconductor Inc., USA
Ekaterina Trofimova , Freescale Semiconductor Inc., USA
pp. 111-118

Language-driven Validation of Pipelined Processors using Satisfiability Solvers (Abstract)

Heon-Mo Koo , University of Florida, USA
Prabhat Mishra , University of Florida, USA
Zhuo Huang , University of Florida, USA
pp. 119-126
Advances in Verification Methodology for Complex Designs

On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling (Abstract)

Andrea Fedeli , TMicroelectronics, Italy
Franco Fummi , University of Verona, Italy
Nicola Bombieri , TMicroelectronics, Italy
pp. 127-132

HW/SW Co-Verification of a RISC CPU using Bounded Model Checking (Abstract)

Rolf Drechsler , University of Bremen, Germany
Ulrich K? , University of Bremen, Germany
Daniel Gro?e , University of Bremen, Germany
pp. 133-137

Retiming Verification Using Sequential Equivalence Checking (Abstract)

Brian Kahne , Freescale Semiconductor Inc, USA
Magdy Abadir , Freescale Semiconductor Inc, USA
pp. 138-142
Author Index

Author Index (PDF)

pp. 143
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