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Fifth International Workshop on Microprocessor Test and Verification (MTV'04) (2004)
Austin, Texas
Sept. 9, 2004 to Sept. 10, 2004
ISSN: 1550-4093
ISBN: 0-7695-2320-X

Acknowledgement (PDF)

pp. viii

Preface (PDF)

pp. vii
Session A: Functional Test Generation

Automatic Test Programs Generation Driven by Internal Performance Counters (Abstract)

E. Sanchez , Politecnico di Torino
W. Lindsay , Intel® Corporation
M. Sonza Reorda , Politecnico di Torino
G. Squillero , Politecnico di Torino
pp. 8-13
Session B: SOC Test

Compact ATPG for Concurrent SOC Testing (Abstract)

Spyros Tragoudas , Southern Illinois University
Arkan Abdulrahman , Southern Illinois University
pp. 16-21

Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores (Abstract)

P. Bernardi , Politecnico di Torino
M. Rebaudengo , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
pp. 22-27
Session C: Modeling and Verification Method

Extreme Formal Modeling (XFM) for Hardware Models (Abstract)

Syed Suhaib , Virginia Polytechnic and State University
David Berner , Institut de Recherche en Informatique et Systèmes Aléatoires
Deepak Mathaikutty , Virginia Polytechnic and State University
Sandeep Shukla , Virginia Polytechnic and State University
pp. 30-35

Formal Specification of an Asynchronous Processor via Action Refinement (Abstract)

Mila Majster-Cederbaum , Universität Mannheim
Xiuli Sun , Chinese Academy of Sciences
Xiaoyu Song , Portland State University
Jinzhao Wu , Universität Mannheim
pp. 36-41
Session D: SAT and Applications

Debugging Sequential Circuits Using Boolean Satisfiability (Abstract)

Rolf Drechsler , University of Bremen
Andreas Veneris , University of Toronto
Alexander Smith , University of Toronto
Magdy Abadir , Freescale Semiconductor, Inc.
Sean Safarpour , University of Toronto
Moayad Fahim Ali , University of Toronto
pp. 44-49

On the Impact of Structural Circuit Partitioning on SAT-Based Combinational Circuit Verification (Abstract)

Marc Herbstritt , Albert-Ludwigs-University
Thomas Kmieciak , Albert-Ludwigs-University
Bernd Becker , Albert-Ludwigs-University
pp. 50-55

PICHAFF² — A Hierarchical Parallel SAT Solver (Abstract)

Tobias Schubert , Albert - Ludwigs - University of Freiburg
Bernd Becker , Albert - Ludwigs - University of Freiburg
pp. 56-61
Session E: Functional Verification

Functional Verification of Pipelined Processors: A Case Study (Abstract)

Nikil Dutt , University of California at Irvine
Yaron Kashai , Verisity Design, Inc.
Prabhat Mishra , University of Florida
pp. 79-84

A Verification Methodology for Reconfigurable Systems (Abstract)

J.-L. Lambert , TNI-Valiosys
M. Borgatti , ST-Microlectronics
G. Pravadelli , Università di Verona
A. Fedeli , ST-Microlectronics
C. Marconcini , Università di Verona
F. Fummi , Università di Verona
I. Moussa , TNI-Valiosys
U. Rossi , ST-Microlectronics
pp. 85-90
Session F: Advanced Test

Identification of Gates for Covering all Critical Paths (Abstract)

Magdy Abadir , Freescale Semiconductor Inc.
Spyros Tragoudas , Southern Illinois University
Brandon Liu , Freescale Semiconductor Inc.
M. Moiz Khan , Southern Illinois University
pp. 92-96

A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide (Abstract)

Xiang Lu , Texas A&M University
Zhuo Li , Texas A&M University
D. M. H. Walker , Texas A&M University
Weiping Shi , Texas A&M University
Wangqi Qiu , Texas A&M University
pp. 97-102

On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design (Abstract)

L.-C. Wang , University of California at Santa Barbara
S. Karako , Freescale Semiconductor Inc.
J. Zeng , Freescale Semiconductor Inc.
M. S. Abadir , Freescale Semiconductor Inc.
G. Vandling , Cadence Design Systems
J. A. Abraham , University of Texas at Austin
pp. 103-109
Special Session G: Micro-Architecture Verification

Micro-Architecture Verification for Microprocessors (PDF)

Laurent Fournier , IBM Labs in Haifa
Eyal Bin , IBM Labs in Haifa
pp. 112-113

Author Index (PDF)

pp. 114
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