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Fifth International Workshop on Microprocessor Test and Verification (MTV'04) (2003)
Hyatt Town Lake Hotel, Austin, Texas
May 29, 2003 to May 30, 2003
ISBN: 0-7695-2045-6
TABLE OF CONTENTS

Preface (PDF)

pp. vii
Session A: Functional Test Generation

null (PDF)

pp. null

DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms (Abstract)

Yoav Katz , IBM Research Laboratory in Haifa
Roy Emek , IBM Research Laboratory in Haifa
Anatoly Koyfman , IBM Research Laboratory in Haifa
Allon Adir , IBM Research Laboratory in Haifa
pp. 3

Modeling IP Responses in Testcase Generation for Systems-on-Chip Verification (Abstract)

Mrinal Bose , Motorola Inc., Austin, TX
Arvind Chodavadia , Motorola Inc., Austin, TX
William R. Jurasz, Jr. , Motorola Inc., Austin, TX
Vlad Zavadsky , Motorola Inc., Austin, TX
Mark H. Nodine , Motorola Inc., Austin, TX
Lincoln R. Nunes , Motorola Inc., Austin, TX
pp. 7
Session B: Special Session, Research at University of Texas and Texas A&M

null (PDF)

pp. null

Testing the Path Delay Faults of ISCAS85 Circuit c6288 (Abstract)

D. M. H. Walker , Texas A&M University
Wangqi Qiu , Texas A&M University
pp. 19

Keynote Speech (PDF)

pp. null
Session C: Issues in Microprocessor Test and Verification

null (PDF)

pp. null

Utilizing Various ADL Facets for Instruction Level CPU Test (Abstract)

Elham Safi , University of Tehran, Iran
Zohreh Karimi , University of Tehran, Iran
Maghsoud Abbaspour , University of Tehran, Iran
Zainalabedin Navabi , University of Tehran, Iran
pp. 38
Session E: Debug and Diagnosis

null (PDF)

pp. null

Automatic Detection of Logic Bugs in Hardware Designs (Abstract)

Alexander Klaiber , Transmeta Corporation
Sinclair Chau , Transmeta Corporation
pp. 47

Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs (Abstract)

Yu-Shen Yang , University of Toronto, ON
Paul Thadikaran , Intel Corporation, Architecture Group, Hillsboro, OR
J. Brandon Liu , University of Toronto, ON
Andreas Veneris , University of Toronto, ON
pp. 54
Session F: SAT and ATPG

null (PDF)

pp. null

Heuristic Backtracking Algorithms for SAT (Abstract)

A. Bhalla , Technical University of Lisbon, Portugal
I. Lynce , Technical University of Lisbon, Portugal
J. Marques-Silva , Technical University of Lisbon, Portugal
J.T. de Sousa , Technical University of Lisbon, Portugal
pp. 69

Tuning the VSIDS Decision Heuristic for Bounded Model Checking (Abstract)

Emmanuel Zarpas , IBM Haifa Research Laboratory, University Campus
Ohad Shacham , IBM Haifa Research Laboratory, University Campus
pp. 75
Session G: Embedded System Validation

null (PDF)

pp. null

A Methodology for Validation of Microprocessors using Equivalence Checking (Abstract)

Nikil Dutt , University of California, Irvine
Prabhat Mishra , University of California, Irvine
pp. 83

A SystemC-based Framework for Properties Incompleteness Evaluation (Abstract)

Massimo Poncino , Universit? di Verona, Italy
Alessandro Fin , Universit? di Verona, Italy
Graziano Pravadelli , Universit? di Verona, Italy
Franco Fummi , Universit? di Verona, Italy
pp. 89
Session H: Simulation Techniques

Systematic Abstractions of Microprocessor RTL models to enhance Simulation Efficiency (Abstract)

Hiren Patel , Virginia Polytechnic and State University, Blacksburg, VA
Debayan Bhaduri , Virginia Polytechnic and State University, Blacksburg, VA
Shekhar Sharad , Virginia Polytechnic and State University, Blacksburg, VA
Syed Suhaib , Virginia Polytechnic and State University, Blacksburg, VA
Madhup Chandra , Virginia Polytechnic and State University, Blacksburg, VA
pp. 103
Session I: Case Study
Session K: High-Level Verification

null (PDF)

pp. null

A Deterministic Globally Asynchronous Locally Synchronous Microprocessor Architecture (Abstract)

Matthew Heath , University of Massachusetts Amherst
Ian Harris , University of Massachusetts Amherst
pp. 119

Author Index (PDF)

pp. 125
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