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Memory Technology, Design and Testin, IEEE International Workshop on (2005)
Taipei, Taiwan
Aug. 3, 2005 to Aug. 5, 2005
ISSN: 1087-4852
ISBN: 0-7695-2313-7

list-reviewer (PDF)

pp. xi

Foreword (PDF)

pp. viii

Zero capacitor embedded memory technology for system on chip (PDF)

S. Okhonin , Innovative Silicon Inc.
P. Fazan , Innovative Silicon Inc.
M.-E. Jones , Innovative Silicon Inc.
pp. 0-0

Foreword (PDF)

pp. viii

Invited Talks (PDF)

pp. xv-xxv
Session T1: Nonvolatile Memory

Novel Self-Convergent Scheme Logic-Process-Based Multilevel/Analog EEPROM Memory (Abstract)

Kung-Hong Lee , National Tsing-Hua University
Shih-Chen Wang , National Tsing-Hua University
Ya-Chin King , National Tsing-Hua University
pp. 3-8

Embedded OTP Fuse in CMOS Logic Process (Abstract)

Ching-Yuan Lin , eMemory Technology Incorporation
Chung-Hung Lin , eMemory Technology Incorporation
Chien-Hung Ho , eMemory Technology Incorporation
Wei-Wu Liao , eMemory Technology Incorporation
Shu-Yueh Lee , eMemory Technology Incorporation
Ming-Chou Ho , eMemory Technology Incorporation
Shih-Chen Wang , eMemory Technology Incorporation
Shih-Chan Huang , eMemory Technology Incorporation
Yuan-Tai Lin , eMemory Technology Incorporation
Charles Ching-Hsiang Hsu , eMemory Technology Incorporation
pp. 13-15

Via-Programmable Read-Only Memory Design for Full Code Coverage Using a Dynamic Bit-Line Shielding Technique (Abstract)

Meng-Fan Chang , National Chiao Tung University and Intellectual Property Library Company
Ding-Ming Kwai , Intellectual Property Library Company
Kuei-Ann Wen , National Chiao Tung University
pp. 16-21

A Nor-Type MLC ROM with Novel Sensing Scheme for Embedded Applications (Abstract)

Star Sung , Taiwan ImagingTek Corporation
Thomas Chang , Vanguard Semiconductor Corporation
JueiLung Chen , Vanguard Semiconductor Corporation
pp. 22-28
Session T2: New Memory Device

Dielectric Tunnel Parameters of CoFe/Al-O/CoFe in MTJ for 1T1MTJ MRAM Applications (Abstract)

Simon C. Li , National Yunlin University of Science and Technology
J. M. Lee , National Yunlin University of Science and Technology
M. F. Shu , National Yunlin University of Science and Technology
J. P. Su , National Yunlin University of Science and Technology
T.-H. Wu , National Yunlin University of Science and Technology
pp. 29-34

A Novel Single Poly-Silicon EEROM Using Trench Floating Gate (Abstract)

Meng-Yi Wu , National Tsing-Hua University
Shin-Chang Feng , National Tsing-Hua University
Ya-Chin King , National Tsing-Hua University
pp. 35-37

An Investigation into Three-Level Ferroelectric Memory (Abstract)

Kamlesh R. Raiter , University of Alberta
Bruce F. Cockburn , University of Alberta
pp. 38-43
Session T3: Design and Test of DRAM

A 1GHz Embedded DRAM Macro and Fully Programmable BIST with At-Speed Bitmap Capability (Abstract)

Valerie Lines , MOSAID Technologies Incorporated
Robert McKenzie , MOSAID Technologies Incorporated
Hak-June Oh , MOSAID Technologies Incorporated
Hong-Beom Pyeon , MOSAID Technologies Incorporated
Matthew Dunn , MOSAID Technologies Incorporated
Susan Palapar , MOSAID Technologies Incorporated
Susan Coleman , MOSAID Technologies Incorporated
Peter Nyasulu , MOSAID Technologies Incorporated
Tony Mai , MOSAID Technologies Incorporated
Seanna Pike , MOSAID Technologies Incorporated
John McCready , MOSAID Technologies Incorporated
Jody Defazio , MOSAID Technologies Incorporated
Jin-Ki Kim , MOSAID Technologies Incorporated
Robert Penchuk , Analog Devices, Inc.
Zvika Greenfield , Analog Devices, Inc.
Fredy Lange , Analog Devices, Inc.
Alberto Mandler , Analog Devices, Inc.
Eric C. Jones , Analog Devices, Inc.
Matthew Silverstein , Analog Devices, Inc.
pp. 47-51

A High Speed BIST Architecture for DDR-SDRAM Testing (Abstract)

Sheng-Chih Shen , National Cheng Kung University
Hung-Ming Hsu , National Cheng Kung University
Yi-Wei Chang , National Cheng Kung University
Kuen-Jong Lee , National Cheng Kung University
pp. 52-57

A Programmable Built-In Self-Test for Embedded DRAMs (Abstract)

Shibaji Banerjee , Indian Institute of Technology - Kharagpur
Dipanwita Roy Chowdhury , Indian Institute of Technology - Kharagpur
Bhargab B. Bhattacharya , Indian Institute of Technology - Kharagpur
pp. 58-63
Session T4: Built-In Self-Test

Full-Speed Field Programmable Memory BIST Supporting Multi-level Looping (Abstract)

Xiaogang Du , Mentor Graphics
Nilanjan Mukherjee , Mentor Graphics
Wu-Tung Cheng , Mentor Graphics
Sudhakar M. Reddy , University of Iowa
pp. 67-71

FSM-Based Programmable Memory BIST with Macro Command (Abstract)

Po-Chang Tsai , National Chung-Hsing University
Sying-Jyan Wang , National Chung-Hsing University
Feng-Ming Chang , National Chung-Hsing University
pp. 72-77

A DFT Architecture for a Dynamic Fault Model of the Embedded Mask ROM of SOC (Abstract)

Yang-Han Lee , Tamkang University
Yih-Guang Jan , Tamkang University
Jei-Jung Shen , Tamkang University
Shian-Wei Tzeng , Tamkang University
Ming-Hsueh Chuang , Tamkang University
Jheng-Yao Lin , Tamkang University
pp. 78-82

A Complete Memory Address Generator for Scan Based March Algorithms (Abstract)

Wei-Lun Wang , Cheng Shiu University
Kuen-Jong Lee , National Cheng Kung University
pp. 83-88

Software Based In-System Memory Test for Highly Available Systems (Abstract)

Amandeep Singh , Sun Microsystems, Inc.
Debashish Bose , Sun Microsystems, Inc.
Sandeep Darisala , Sun Microsystems, Inc.
pp. 89-94
Session T5: Memory Test and Repair

A Systematic Approach to Reducing Semiconductor Memory Test Time in Mass Production (Abstract)

Jen-Chieh Yeh , National Tsing Hua University
Shyr-Fen Kuo , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
Chih-Tsun Huang , National Tsing Hua University
Chao-Hsun Chen , Winbond Electronics Corp.
pp. 97-102

Impact of Stresses on the Fault Coverage of Memory Tests (Abstract)

Said Hamdioui , Delft University of Technology
Zaid Al-Ars , Delft University of Technology
Ad J. van de Goor , Delft University of Technology
Rob Wadsworth , ST Microlelctronics
pp. 103-108

DFT Techniques for Memory Macro with Built-In ECC (Abstract)

Keiichi Kushida , Toshiba Corporation
Nobuaki Otsuka , Toshiba Corporation
Osamu Hirabayashi , Toshiba Corporation
Yasuhisa Takeyama , Toshiba Corporation
pp. 109-114

An Error Detection and Correction Scheme for RAMs with Partial-Write Function (Abstract)

Jin-Fu Li , National Central University
Yu-Jane Huang , National Central University
pp. 115-120

A BIRA Algorithm for Embedded Memories with 2-D Redundancy (Abstract)

Shyue-Kung Lu , Fu Jen Catholic University
Yu-Cheng Tsai , Fu Jen Catholic University
Shih-Chang Huang , Fu Jen Catholic University
pp. 121-126
Session T6: SRAM Design and Characterization

Distributed Data-Retention Power Gating Techniques for Column and Row Co-Controlled Embedded SRAM (Abstract)

Chung-Hsien Hua , National Chiao-Tung University
Tung-Shuan Cheng , National Chiao-Tung University
Wei Hwang , National Chiao-Tung University
pp. 129-134

A Low-Power SRAM Design Using Quiet-Bitline Architecture (Abstract)

Shin-Pao Cheng , National Tsing-Hua University
Shi-Yu Huang , National Tsing-Hua University
pp. 135-139

Measurement and Characterization of 6T SRAM Cell Current (Abstract)

Ching-Hua Hsiao , Intellectual Property Library Company and National Chiao Tung University
Ding-Ming Kwai , Intellectual Property Library Company
pp. 140-145

Reliability Enhancement of CMOS SRAMs (Abstract)

Chin-Long Wey , National Central University
Meng-Yao Liu , National Central University
Shaolei Quan , Michigan State University
pp. 146-151
Author Index

Author Index (PDF)

pp. 153-154
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