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Memory Technology, Design and Testin, IEEE International Workshop on (2004)
San Jose, California, USA
Aug. 9, 2004 to Aug. 10, 2004
ISSN: 1087-4852
ISBN: 0-7695-2193-2
TABLE OF CONTENTS

Fast error-correcting circuits for fault-tolerant memory (PDF)

E. Ou , VLSI Group, Harvard Univ., Cambridge, MA, USA
W. Yang , VLSI Group, Harvard Univ., Cambridge, MA, USA
pp. 8-12

Tag skipping technique using WTS buffer for optimal low power cache design (PDF)

A. Akaaboune , Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
N. Botros , Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
J. Alghazo , Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
pp. 13-18

SF-LRU cache replacement algorithm (PDF)

J. Alghazo , Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
A. Akaaboune , Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
N. Botros , Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
pp. 19-24

The effectiveness of the scan test and its new variants (PDF)

A.J. van de Goor , Fac. of Electr. Eng., Math. & Comput. Sci., Delft Univ. of Technol., Netherlands
S. Hamdioui , Fac. of Electr. Eng., Math. & Comput. Sci., Delft Univ. of Technol., Netherlands
Z. Al-Ars , Fac. of Electr. Eng., Math. & Comput. Sci., Delft Univ. of Technol., Netherlands
pp. 26-31

Markov models of fault-tolerant memory systems under SEU (PDF)

L. Schiano , Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
M. Ottavi , Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
F. Lombardi , Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
pp. 38-43

Tutorial on magnetic tunnel junction magnetoresistive random-access memory (PDF)

B.F. Cockburn , Dept. OF Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada
pp. 46-51

The state-of-art and future trends in testing embedded memories (PDF)

S. Hamdioui , Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
G. Gaydadjiev , Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
A.J. van de Goor , Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 54-59

Built-in self-test and repair (BISTR) techniques for embedded RAMs (PDF)

Shyue-Kung Lu , Dept. of Electron. Eng., Fu Jen Catholic Univ., Taipei, Taiwan
Shih-Chang Huang , Dept. of Electron. Eng., Fu Jen Catholic Univ., Taipei, Taiwan
pp. 60-64
Introduction
Session 1: Special Session

null (PDF)

pp. null
Session 2: Fast ECC and Efficient Cache Controllers

null (PDF)

pp. null

Fast Error-Correcting Circuits for Fault-Tolerant Memory (Abstract)

Elaine Ou , Harvard University
Woodward Yang , Harvard University
pp. 8-12

Tag Skipping Technique Using WTS Buffer for Optimal Low Power Cache Design (Abstract)

Adil Akaaboune , Southern Illinois University at Carbondale
Nazeih Botros , Southern Illinois University at Carbondale
Jaafar Alghazo , Southern Illinois University at Carbondale
pp. 13-18

SF-LRU Cache Replacement Algorithm (Abstract)

Jaafar Alghazo , Southern Illinois University at Carbondale
Adil Akaaboune , Southern Illinois University at Carbondale
Nazeih Botros , Southern Illinois University at Carbondale
pp. 19-24
Session 3: Memory Fault Coverage and Test Analysis

null (PDF)

pp. null

The Effectiveness of the Scan Test and Its New Variants (Abstract)

Ad J. van de Goor , Delft University of Technology
Said Hamdioui , Delft University of Technology
Zaid Al-Ars , Delft University of Technology
pp. 26-31

Influence of Bit Line Twisting on the Faulty Behavior of DRAMs (Abstract)

Zaid Al-Ars , CatRam Solutions, Delft University of Technology and Infineon Technologies
Martin Herzog , Infineon Technologies
Ivo Schanstra , Infineon Technologies
Ad J. van de Goor , Delft University of Technology
pp. 32-37

Markov Models of Fault-Tolerant Memory Systems under SEU (Abstract)

Luca Schiano , Northeastern University
Marco Ottavi , Northeastern University
Fabrizio Lombardi , Northeastern University
pp. 38-43
Session 4: Special Session

null (PDF)

pp. null
Session 5: Embedded Memory Test Trends and Future

null (PDF)

pp. null

The State-of-Art and Future Trends in Testing Embedded Memories (Abstract)

Said Hamdioui , Delft University of Technology
Georgi Gaydadjiev , Delft University of Technology
Ad J. van de Goor , Delft University of Technology
pp. 54-59

Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs (Abstract)

Shyue-Kung Lu , Fu Jen Catholic University
Shih-Chang Huang , Fu Jen Catholic University
pp. 60-64

A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories (Abstract)

Li-Ming Denq , National Tsing Hua University
Rei-Fu Huang , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
Yeong-Jar Chang , Industrial Technology Research Institute
Wen-Ching Wu , Industrial Technology Research Institute
pp. 65-69
Session 6: Industrial Practices on BIST, BISD and BISR

null (PDF)

pp. null

Micro Programmable Built-In Self Repair for SRAMs (Abstract)

R. Zappa , STMicroelectronics
C. Selva , STMicroelectronics
D. Rimondi , STMicroelectronics
C. Torelli , STMicroelectronics
M. Crestan , STMicroelectronics
G. Mastrodomenico , STMicroelectronics
L. Albani , STMicroelectronics
pp. 72-77

A Programmable Built-in Self-Diagnosis for Embedded SRAM (Abstract)

Carolina Selva , STMicroelectronics
Cosimo Torelli , STMicroelectronics
Danilo Rimondi , STMicroelectronics
Rita Zappa , STMicroelectronics
Stefano Corbani , STMicroelectronics
Giovanni Mastrodomenico , STMicroelectronics
Lara Albani , STMicroelectronics
pp. 84-89
Session 7: EDA Solutions to Test and Repair Memories

null (PDF)

pp. null

An Integrated Memory Self Test and EDA Solution (Abstract)

R. Dean Adams , Magma Design Automation
Robert Abbott , Magma Design Automation
Xiaoliang Bai , Magma Design Automation
Dwayne Burek , Magma Design Automation
Eric MacDonald , University of Texas at El Paso
pp. 92-95

A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs (Abstract)

Saman Adham , LogicVision, Inc.
Benoit Nadeau-Dostie , LogicVision, Inc.
pp. 98-101
Session 8: Making Memories More Reliable

null (PDF)

pp. null

Embedded Memory Reliability: The SER Challenge (Abstract)

N. Derhacobian , Virage Logic Corporation
V. A. Vardanian , Virage Logic Corporation
Y. Zorian , Virage Logic Corporation
pp. 104-110

Do We Need Anything More Than Single Bit Error Correction (ECC)? (Abstract)

Michael Spica , Intel Corporation
TM Mak , Intel Corporation
pp. 111-116

Redundancy & It?s Not Just for Defects Anymore (Abstract)

Rob Aitken , Artisan Components
pp. 117-120
Author Index

Author Index (PDF)

pp. 121
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