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Memory Technology, Design and Testin, IEEE International Workshop on (2003)
San Jose, California
July 28, 2003 to July 29, 2003
ISBN: 0-7695-2004-9
Plenary Session
MTDT Message (PDF)
pp. null
Keynote Address
Session 1: DRAM for Leading Edge Applications
Betty Prince , Memory Strategies International
pp. 7
Bruce F. Cockburn , University of Alberta
Jes?s Hern?ndez Tapia , University of Alberta
Duncan G. Elliott , University of Alberta
pp. 14
Youhei Zenda , Osaka University
Koji Nakamae , Osaka University
Hiromu Fujioka , Osaka University
pp. 20
Session 2: Fault Analysis and Test Generation and Verification
Zaid Al-Ars , Delft University of Technology
Ad J. van de Goor , Delft University of Technology
pp. 27
Zaid Al-Ars , Delft University of Technology
Said Hamdioui , Delft University of Technology
Ad J. van de Goor , Delft University of Technology
pp. 33
Session 3: Enhanced Testing Techniques
Joerg Vollrath , Infineon Technologies
pp. 43
Baosheng Wang , University of British Columbia
Josh Yang , University of British Columbia
Andr? Ivanov , University of British Columbia
pp. 47
Rei-Fu Huang , National Tsing Hua University
Li-Ming Denq , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
Jin-Fu Li , National Central University
pp. 53
Session 4: Panel: Are All the Memory BIST Challenges Solved?
Session 5: Memory Roadmap, Yield and Optimization
Roger Barth , Intel Corporation
pp. 61
M. Choi , University of Missouri-Rolla
N. Park , Oklahoma State University
F. Lombardi , Northeastern University
Y.B. Kim , Northeastern University
V. Piuri , University of Milan
pp. 64
Session 6: Memory Design Techniques
Jean-Michel Daga , ATMEL, Zone Industrielle
Caroline Papaix , ATMEL, Zone Industrielle
Emmanuel Racape , ATMEL, Zone Industrielle
Marylene Combe , ATMEL, Zone Industrielle
Vincent Sialelli , ATMEL, Zone Industrielle
Jeanine Guichaoua , ATMEL, Zone Industrielle
pp. 81
Session 7: Special Session
Author Index
Author Index (PDF)
pp. 95
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