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Memory Technology, Design and Testin, IEEE International Workshop on (2003)
San Jose, California
July 28, 2003 to July 29, 2003
ISSN: 1087-4852
ISBN: 0-7695-2004-9
TABLE OF CONTENTS
Introduction
Plenary Session

MTDT Message (PDF)

pp. null
Keynote Address
Session 1: DRAM for Leading Edge Applications

Application Specific DRAMs Today (Abstract)

Betty Prince , Memory Strategies International
pp. 7

A Multilevel DRAM with Hierarchical Bitlines and Serial Sensing (Abstract)

Duncan G. Elliott , University of Alberta
Jes?s Hern?ndez Tapia , University of Alberta
Bruce F. Cockburn , University of Alberta
pp. 14

Cost Optimum Embedded DRAM Design by Yield Analysis (Abstract)

Youhei Zenda , Osaka University
Koji Nakamae , Osaka University
Hiromu Fujioka , Osaka University
pp. 20
Session 2: Fault Analysis and Test Generation and Verification

Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes (Abstract)

Ad J. van de Goor , Delft University of Technology
Zaid Al-Ars , Delft University of Technology
pp. 27

A Fault Primitive Based Analysis of Linked Faults in RAMs (Abstract)

Ad J. van de Goor , Delft University of Technology
Zaid Al-Ars , Delft University of Technology
Said Hamdioui , Delft University of Technology
pp. 33
Session 3: Enhanced Testing Techniques

Output Timing Measurement Using an Idd Method (Abstract)

Joerg Vollrath , Infineon Technologies
pp. 43

Reducing Test Time of Embedded SRAMs (Abstract)

Andr? Ivanov , University of British Columbia
Baosheng Wang , University of British Columbia
Josh Yang , University of British Columbia
pp. 47

A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories (Abstract)

Jin-Fu Li , National Central University
Rei-Fu Huang , National Tsing Hua University
Cheng-Wen Wu , National Tsing Hua University
Li-Ming Denq , National Tsing Hua University
pp. 53
Session 4: Panel: Are All the Memory BIST Challenges Solved?
Session 5: Memory Roadmap, Yield and Optimization

ITRS Commodity Memory Roadmap (Abstract)

Roger Barth , Intel Corporation
pp. 61

Optimal Spare Utilization in Repairable and Reliable Memory Cores (Abstract)

V. Piuri , University of Milan
M. Choi , University of Missouri-Rolla
Y.B. Kim , Northeastern University
F. Lombardi , Northeastern University
N. Park , Oklahoma State University
pp. 64
Session 6: Memory Design Techniques

A 40ns Random Access Time Low Voltage 2Mbits EEPROM Memory for Embedded Applications (Abstract)

Caroline Papaix , ATMEL, Zone Industrielle
Marylene Combe , ATMEL, Zone Industrielle
Emmanuel Racape , ATMEL, Zone Industrielle
Jean-Michel Daga , ATMEL, Zone Industrielle
Vincent Sialelli , ATMEL, Zone Industrielle
Jeanine Guichaoua , ATMEL, Zone Industrielle
pp. 81
Session 7: Special Session
Author Index

Author Index (PDF)

pp. 95
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