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Memory Technology, Design and Testin, IEEE International Workshop on (2002)
Isle of Bendor, France
July 10, 2002 to July 12, 2002
ISSN: 1087-4852
ISBN: 0-7695-1617-3
TABLE OF CONTENTS
Introduction

TTTC Information (PDF)

pp. 180
Keynote Address
Session B: Memory BIST Analysis and Application

A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques (Abstract)

M. Rebaudengo , Politecnico di Torino
A. Fudoli , STMicroelectronics
V. Tancorre , STMicroelectronics
F. Corno , Politecnico di Torino
D. Appello , STMicroelectronics
M. Sonza Reorda , Politecnico di Torino
pp. 12

A Scan-Bist Environment for Testing Embedded Memories (Abstract)

F. Karimi , LTX Corporation
F. Lombardi , Northeastern University
pp. 17
Session C: Memory ECC and Soft Errors

Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories (Abstract)

B. Riccò , University of Bologna
C. Metra , University of Bologna
D. Rossi , University of Bologna
pp. 27

High Speed 15 ns 4 Mbits SRAM for Space Application (Abstract)

Patrick Delaunay , Atmel Corporation
Olivier Husson , Atmel Corporation
Bernard Coloma , Atmel Corporation
pp. 32
Session D: High Reliability in Railway and Automotive Systems

Fault Tolerant Insertion and Verification: A Case Study (Abstract)

Diego De Costantini , Centro Ricerche FIAT
Alberto Manzone , Centro Ricerche FIAT
pp. 44

Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems (Abstract)

Cecilia Metra , University of Bologna
Luca Schiano , University of Bologna
Diego Marino , Alstom Transport Spa
pp. 49
Session E: Embedded Memory Yield Enhancement

A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories (Abstract)

Cheng-Wen Wu , National Tsing Hua University
Rei-Fu Huang , National Tsing Hua University
Jen-Chieh Yeh , National Tsing Hua University
Jin-Fu Li , National Tsing Hua University
pp. 68
Keynote Address
Session 1: Embedded Memory Systems and Test Optimization

Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch (Abstract)

Robert Gibbins , Nortel Networks
Yuejian Wu , Nortel Networks
Thomas Eckenrode , IBM Microelectronics
Michael Ouellette , IBM Microelectronics
R. Dean Adams , IBM Microelectronics
pp. 83

Adder Merged DRAM Architecture (Abstract)

Masashi Hashimoto , Cadence Design Systems
pp. 88
Session 2: Memory Test Strategies

March SS: A Test for All Static Simple RAM Faults (Abstract)

Said Hamdioui , Intel Corporation and Delft University of Technology
Mike Rodgers , Intel Corporation
Ad J. van de Goor , Delft University of Technology
pp. 95

Random Testing of Multi-Port Static Random Access Memories (Abstract)

F. Karimi , LTX Corporation
F. J. Meyer , Northeastern University
F. Lombardi , Northeastern University
pp. 101
Session 3: Fault Modeling

A Fault Modeling Technique to Test Memory BIST Algorithms (Abstract)

Raja Venkatesh , Paxonet Communications
Sailesh Kumar , Paxonet Communications
Joji Philip , Paxonet Communications
Sunil Shukla , Paxonet Communications
pp. 109

Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM (Abstract)

Michael Redeker , University of Alberta
Bruce F. Cockburn , University of Alberta
Sue Ann Ung , University of Alberta
Yunan Xiang , University of Alberta
Duncan G. Elliott , University of Alberta
pp. 117

An Investigation into Crosstalk Noise in DRAM Structures (Abstract)

Duncan G. Elliott , University of Alberta
Bruce F. Cockburn , University of Alberta
Michael Redeker , University of Hanover
pp. 123
Keynote Address
Session 5: EPROM/EEPROM Design

An Automated Design Methodology for EEPROM Cell (ADE) (Abstract)

H. Aziza , ICF/L2MP-UMR CNRS and ST-Microelectronics
J. M. Portal , ICF/L2MP-UMR CNRS
D. Née , ST-Microelectronics
L. Forli , ICF/L2MP-UMR CNRS and ST-Microelectronics
pp. 137
Session 6: Process Technology and Reliability

Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC) (Abstract)

J-P. Carrere , STMicroelectronics
S. Naudet , STMicroelectronics
P-J. Goirand , STMicroelectronics
T. Devoivre , STMicroelectronics
F. Guyader , STMicroelectronics
P. Gayet , STMicroelectronics
F. Lalanne , STMicroelectronics
D. Heslinga , PHILIPS Semiconductors
F. Pico , STMicroelectronics
P. Vannier , STMicroelectronics
R. Palla , STMicroelectronics
D. Roy , STMicroelectronics
N. Planes , STMicroelectronics
A. VandeGoor , PHILIPS Semiconductors
P. Ferreira , STMicroelectronics
M. Lunenborg , PHILIPS Semiconductors
O. Hinsinger , STMicroelectronics
W. J. Toren , PHILIPS Semiconductors
Y. Rody , PHILIPS Semiconductors
I. Thomas , STMicroelectronics
T. Berger , STMicroelectronics
C. Julien , STMicroelectronics
B. Borot , STMicroelectronics
D. Duca , STMicroelectronics
M. Haond , STMicroelectronics
pp. 157

Converting an Embedded Low-Power SRAM from Bulk to PD-SOI (Abstract)

Philippe Flatresse , ST Microelectronics
Mario R. Casu , Politecnico di Torino
pp. 163

Decreasing EEPROM Programming Bias With Negative Voltage, Reliability Impact (Abstract)

R. Bouchakour , L2MP/Polytech-UMR CNRS
J. Razafindramora , L2MP/Polytech-UMR CNRS
P. Canet , L2MP/Polytech-UMR CNRS
R. Laffont , L2MP/Polytech-UMR CNRS and ST-Microelectronics
J. M. Mirabel , ST-Microelectronics
pp. 168
Session 7: Advanced Memory Technologies Panel
Author Index

Author Index (PDF)

pp. 179
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