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Memory Technology, Design and Testin, IEEE International Workshop on (2001)
San Jose, California
Aug. 6, 2001 to Aug. 7, 2001
ISBN: 0-7695-1242-9
TABLE OF CONTENTS

TTTC Information (PDF)

pp. 106
Session 1: Memory Design

Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme (Abstract)

KwangMyoung Rho , Korea Advanced Institute of Science and Technology (KAIST)
Kwyro Lee , Korea Advanced Institute of Science and Technology (KAIST)
Kyung-Saeng Kim , Korea Advanced Institute of Science and Technology (KAIST)
pp. 0009

Design of an Embedded Fully-Depleted SOI SRAM (Abstract)

Raymond J. Sung , University of Alberta
Bruce F. Cockburn , University of Alberta
John C. Koob , University of Alberta
Tyler L. Brandon , University of Alberta
Duncan G. Elliott , University of Alberta
pp. 0013
Session 2: Memory BIST

A P1500 Compliant Programable BistShell for Embedded Memories (Abstract)

Robert Beurze , ED&T/Test
Sunil Kumar , Philips Semiconductors
G. S. Visweswaran , IIT-Delhi
Sandeep Koranne , ED&T/Test
Tom Waayers , ED&T/Test
pp. 0021

BIST-Based Bitfail Mapping of an Embedded DRAM (Abstract)

Brian R. Kessler , International Business Machines Corp.
Rex Kho , International Business Machines Corp.
Jeffrey Dreibelbis , International Business Machines Corp.
Joshua S. McCloy , International Business Machines Corp.
Tim McMahon , International Business Machines Corp.
pp. 0029
Session 5: Redundancy and Error Control

A Method to Caculate Redundancy Coverage for FLASH Memory (Abstract)

S. Matarrese , STMicroelectronics
L. Fasoli , STMicroelectronics
pp. 0041

An Error Control Code Scheme for Multilevel Flash Memories (Abstract)

Guido Torelli , University of Pavia
Rino Micheloni , STMicroelectronics
Osama Khouri , STMicroelectronics
Stefano Gregori , University of Pavia
pp. 0045

An Approach for Evaluation of Redunancy Analysis Algorithms (Abstract)

V. Vardanian , Virage Logic Int.
Y. Zorian , Virage Logic Corp.
S. Shoukourian , Virage Logic Int.
pp. 0051
Session 6: Fault Models and Multi-Port SRAM Testing

Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests (Abstract)

Ad J. van de Goor , Delft University of Technology
Zaid Al-Ars , Delft University of Technology
pp. 0059

Realistic Fault Models and Test Procedures for Multi-Port SRAMs (Abstract)

Mike Rodgers , Intel Corporation
Said Hamdioui , Intel Corporation
Ad J. van de Goor , Delft University of Technology
David Eastwick , Intel Corporation
pp. 0065

A Parallel Approach for Testing Multi-Port Static Random Access Memories (Abstract)

F. Lombardi , Northeastern University
S. Irrinki , LSI Logic Inc.
F. Karimi , Northeastern University
T. Crosby , LSI Logic Inc.
pp. 0073
Session 7: Verification and Test

Equivalence Checking a 256MB SDRAM (Abstract)

Simon Napper , InnoLogic Systems Inc.
Dian Yang , InnoLogic Systems Inc.
pp. 0085

Testing Carry Logic Modules of SRAM-based FPGAs (Abstract)

Jian Xu , University of Alberta
Pieter Trouborst , Nortel Networks
Xiaoling Sun , University of Alberta
pp. 0091

Low Output Resistance Charge Pump for Flash Memory Programming (Abstract)

Osama Khouri , STMicroelectronics
Rino Micheloni , STMicroelectronics
Stefano Gregori , University of Pavia
Guido Torelli , University of Pavia
Dario Soltesz , University of Pavia
pp. 0099

Author Index (PDF)

pp. 0105
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