Message from the Chairs (PDF)
Conference Committee (PDF)
TTTC Information (PDF)
Orthogonal Transpose-RAM Cell Array Architecture with Alternate Bit-Line To Bit-Line Contact Scheme (Abstract)
Design of an Embedded Fully-Depleted SOI SRAM (Abstract)
A P1500 Compliant Programable BistShell for Embedded Memories (Abstract)
BIST-Based Bitfail Mapping of an Embedded DRAM (Abstract)
A Method to Caculate Redundancy Coverage for FLASH Memory (Abstract)
An Error Control Code Scheme for Multilevel Flash Memories (Abstract)
An Approach for Evaluation of Redunancy Analysis Algorithms (Abstract)
Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests (Abstract)
Realistic Fault Models and Test Procedures for Multi-Port SRAMs (Abstract)
A Parallel Approach for Testing Multi-Port Static Random Access Memories (Abstract)
Equivalence Checking a 256MB SDRAM (Abstract)
Testing Carry Logic Modules of SRAM-based FPGAs (Abstract)
Low Output Resistance Charge Pump for Flash Memory Programming (Abstract)
Author Index (PDF)