The Community for Technology Leaders
Memory Technology, Design and Testin, IEEE International Workshop on (2000)
San Jose, California
Aug. 7, 2000 to Aug. 8, 2000
ISSN: 1087-4852
ISBN: 0-7695-0689-5
Plenary Session

Welcome Message (PDF)

pp. null
Session 1: Failure Mechanism/Defects: Chair: Betty Prince, Memory Strategy International
Session 2: Flash/EEPROM Design: Chair: Alex Shubat, Virage Logic

Hierarchical Sector Biasing Organization for Flash Memories (Abstract)

Rino Micheloni , STMicroelectronics
Matteo Zammattio , STMicroelectronics
Giovanni Campardo , STMicroelectronics
Osama Khouri , University of Pavia
Guido Torelli , University of Pavia
pp. 29

Fast Voltage Regulator for Multilevel Flash Memories (Abstract)

Osama Khouri , STMicroelectronics and University of Pavia
Rino Micheloni , STMicroelectronics
Stefano Gregori , University of Pavia
Guido Torelli , University of Pavia
pp. 34

Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions (Abstract)

Jeanine Guichaoua , ATMEL ROUSSETRANCE
Daniel Auvergne , Montpellier II University
pp. 39
Session 3: New Ideas: Chair: Fabrizio Lombardi, Northeastern University

Windowed MRAM Sensing Scheme (Abstract)

Ruili Zhang , Texas Instruments
William C. Black Jr , Iowa State University
Marwan M. Hassoun , Iowa State University
pp. 47
Session 4
Session 5: Test and Yield: Chair: Robert Evans, Mosaid
Session 6: Memory Testing and Built-in Self-Test: Chair: Swamy Irrinki, LSI Logic

March Tests for Realistic Faults in Two-Port Memories (Abstract)

Said Hamdioui , Delft University of Technology and Intel Corporation
Ad J. van de Goor , Delft University of Technology
Mike Rodgers , Intel Corporation
David Eastwick , Intel Corporation
pp. 73

A Simple Built-In Self Test For Dual Ported SRAMs (Abstract)

Khoan Truong , Cadence Design Systems, Inc.
pp. 79

Using GLFSRs for Pseudo-Random Memory BIST (Abstract)

Michael Redeker , University of Hannover
Markus Rudack , University of Hannover
Thomas Lobbe , University of Hannover
Dirk Niggemeyer , University of Illinois at Urbana-Champaign
pp. 85
Invited Address
Session 7: Memory Design: Chair: Robert Gibbins, Nortel

66MHz 2.3M Ternary Dynamic Content Addressable Memory (Abstract)

Valerie Lines , Mosaid Technologies Incorporated
Abdullah Ahmed , Mosaid Technologies Incorporated
Peter Ma , Mosaid Technologies Incorporated
Stanley Ma , Mosaid Technologies Incorporated
Robert McKenzie , Mosaid Technologies Incorporated
Hong-Seok Kim , Mosaid Technologies Incorporated
Cynthia Mar , Mosaid Technologies Incorporated
pp. 101

A Low Voltage Embedded Single Port SRAM Generator in a 0.18?m Standard CMOS Process (Abstract)

C. Frey , ST Microelectronics
F. Genevaux , ST Microelectronics
C. Issartel , ST Microelectronics
D. Turgis , ST Microelectronics
Jp. Schoellkopf , ST Microelectronics
pp. 106
Session 8: Diagnosis: Chair: Sharon Murray, Medtronic Micro-Rel

Diagnostic Testing of Embedded Memories Based on Output Tracing (Abstract)

Dirk Niggemeyer , University of Illinois at Urbana-Champaign
Elizabeth M. Rudnick , University of Illinois at Urbana-Champaign
Michael Redeker , University of Hannover
pp. 113

Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories (Abstract)

Kamran Zarrineh , IBM Microelectronics
R. Dean Adams , IBM Microelectronics
Aneesha P . Deo , State University of New York at Buffalo
pp. 119

Crosstalk in Deep Submicron DRAMs (Abstract)

Zemo Yang , Santa Clara University
Samiha Mourad , Santa Clara University
pp. 125

Author Index (PDF)

pp. 131
90 ms
(Ver 3.3 (11022016))