CSDL - 1999 IEEE International Workshop on Memory Technology, Design, and Testing - Table of Contents

Memory Technology, Design and Testin, IEEE International Workshop on (1999)

San Jose, California

Aug. 9, 1999 to Aug. 10, 1999

ISSN: 1087-4852

ISBN: 0-7695-0259-8

TABLE OF CONTENTS

Message from the General Chair (PDF)

pp. vii

Message from the Technical Program Chair (PDF)

pp. viii

Conference Committee (PDF)

pp. ix

Keynote Address (PDF)

pp.

Session I: Tutorial on Low Power SRAMs

Low Power SRAMs for Battery Operation (PDF)

Martin Margala , University of Alberta

pp. 6

Session II: Architecture and Applications

Computing in Memory Architectures for Digital Image Processing (Abstract)

Luke Roth Lee Coraor , Pennsylvania State University

David Landis , Pennsylvania State University

Paul Hulina , Pennsylvania State University

Scott Deno , Pennsylvania State University

pp. 8

Unbalanced Cache Systems (Abstract)

David L. Rhodes , United States Army and Princeton University

Wayne Wolf , Princeton University

pp. 16

The Dynamic Associative Access Memory Chip and Its Application to SIMD Processing and Full-Text Database Retrieval (Abstract)

G. Lipovski

C. Yu

pp. 24

Session III: Diagnosis and Yield

Failure Mechanisms Detected in Memory Chips during Routine Construction Analysis (Abstract)

Sue Brown , Chipworks Incorporated

Jeff Campbell , Chipworks Incorporated

Sherri Griffin , Chipworks Incorporated

Dick James , Chipworks Incorporated

Ray Haythornthwaite , Chipworks Incorporated

pp. 34

Interconnect Diagnosis of Bus-Connected Multi-RAM Systems _ (Abstract)

Jun Zhao , Texas A&M University

Fred J. Meyer , Northeastern University

Fabrizio Lombardi , Northeastern University

pp. 40

Determining Redundancy Requirements for Memory Arrays with Critical Area Analysis (Abstract)

Hpl Inc.

pp. 48

Design Validation of .18 um 1 Ghz Cache and Register Arrays (Abstract)

Doug Malone , IBM Corp.

pp. 54

Session IV: Tutorial on SDRAMs

Tutorial: Characterizing SDRAMS (Abstract)

Joerg Vollrath , White Oak Semiconductor

pp. 62

Session V: Memory Testing topics

Built In Self Test for Ring Addressed FIFOs with Transparent Latches (Abstract)

Larry Fenstermaker , Lucent Technologies

Ilyoung Kim , Lucent Technologies

Jim Lewandowski , Lucent Technologies

Jeffrey J. Nagy , Lucent Technologies

pp. 72

A Fast Test to Generate Flash Memory Threshold Voltage Distribution Map (Abstract)

Raju Khubchandani , MOSAID Technologies, Inc.

pp. 78

Modeling and Testing Transistor Faults in Content-Addressable Memories (Abstract)

Piotr R. Sidorowicz , University of Waterloo

pp. 83

Designing a Memory Module Tester (Abstract)

Daniel P. Van der Velde , Delft University of Technology

A.J. v.d. Goor , Delft University of Technology

pp. 91

Session VI: Special Session

Panel on Memories, IP and System-on-a-Chip (PDF)

Panelists: R. Dean Adams

Adam Kablanian

Dhrumil Gandhi

J.W. Smith

pp. 0

Session VII: New Ideas in Technology and Design

A Comparative Simulation Study of Four Multilevel DRAMs (Abstract)

Gershom Birk , University of Alberta

Duncan G. Elliott , University of Alberta

Bruce F. Cockburn , University of Alberta

pp. 102

The Potential of Carbon-Based Memory Systems (Abstract)

Mark Brehob , Michigan State University

Richard Enbody , Michigan State University

pp. 110

Low-Power SRAM Circuit Design (Abstract)

Martin Margala , University of Alberta

pp. 115

A Tribute to Graphics Drams (Abstract)

Betty Prince , Memory Strategies International

pp. 123

Author Index (PDF)

pp. 131