Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing (PDF)

Message from the General Chair (PDF)

Message from the Technical Program Chair (PDF)

Conference Committee (PDF)

Keynote Address (PDF)

Low Power SRAMs for Battery Operation (PDF)

Computing in Memory Architectures for Digital Image Processing (Abstract)

Unbalanced Cache Systems (Abstract)

The Dynamic Associative Access Memory Chip and Its Application to SIMD Processing and Full-Text Database Retrieval (Abstract)

Failure Mechanisms Detected in Memory Chips during Routine Construction Analysis (Abstract)

Interconnect Diagnosis of Bus-Connected Multi-RAM Systems _ (Abstract)

Determining Redundancy Requirements for Memory Arrays with Critical Area Analysis (Abstract)

Design Validation of .18 um 1 Ghz Cache and Register Arrays (Abstract)

Tutorial: Characterizing SDRAMS (Abstract)

Built In Self Test for Ring Addressed FIFOs with Transparent Latches (Abstract)

A Fast Test to Generate Flash Memory Threshold Voltage Distribution Map (Abstract)

Modeling and Testing Transistor Faults in Content-Addressable Memories (Abstract)

Designing a Memory Module Tester (Abstract)

Panel on Memories, IP and System-on-a-Chip (PDF)

A Comparative Simulation Study of Four Multilevel DRAMs (Abstract)

The Potential of Carbon-Based Memory Systems (Abstract)

Low-Power SRAM Circuit Design (Abstract)

A Tribute to Graphics Drams (Abstract)

Author Index (PDF)