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Memory Technology, Design and Testin, IEEE International Workshop on (1997)
San Jose, CA
Aug. 11, 1997 to Aug. 12, 1997
ISSN: 1087-4852
ISBN: 0-8186-8099-7
TABLE OF CONTENTS

Welcome Message (PDF)

pp. vii
Keynote Address
Architectures

A low cost, high performance three-dimensional memory module technology (Abstract)

G. Rinne , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
P. Franzon , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
V. Rogers , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
A. Glaser , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
M. Roberson , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
C.K. Williams , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
M. Nakkar , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 2

High speed circuit techniques in a 150 MHz 64 M SDRAM (Abstract)

C. Mar , MOSAID Technol. Inc., Canada
S. Miyamoto , MOSAID Technol. Inc., Canada
V. Lines , MOSAID Technol. Inc., Canada
Y. Murashima , MOSAID Technol. Inc., Canada
M. Abou-Seido , MOSAID Technol. Inc., Canada
A. Achyuthan , MOSAID Technol. Inc., Canada
S. Sakuma , MOSAID Technol. Inc., Canada
pp. 8
Fault Modeling and Manufacturing

An analysis of (linked) address decoder faults (Abstract)

G.N. Gaydadjiev , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
A.J. van de Goor , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 13

SRAM yield estimation in the early stage of the design cycle (Abstract)

T. Chen , Sun Microsyst., SPARC Technol. Bus., Mountain View, CA, USA
Von-Kyoung Kim , Sun Microsyst., SPARC Technol. Bus., Mountain View, CA, USA
pp. 21

False write through and un-restored write electrical level fault models for SRAMs (Abstract)

E.S. Cooley , Dartmouth's Thayer Sch. of Eng., Hanover, NH, USA
R.D. Adams , Dartmouth's Thayer Sch. of Eng., Hanover, NH, USA
pp. 27

A defect-tolerant DRAM employing a hierarchical redundancy scheme, built-in self-test and self-reconfiguration (Abstract)

D. Niggemeyer , Lab. fur Informationstechnol., Hannover Univ., Germany
M. Redeker , Lab. fur Informationstechnol., Hannover Univ., Germany
J. Otterstedt , Lab. fur Informationstechnol., Hannover Univ., Germany
pp. 33
Tools

Formal verification of memory arrays using symbolic trajectory evaluation (Abstract)

M. Pandey , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
R.E. Bryant , Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 42

A product development flow with metrics for memory designs (Abstract)

K.S. Rao , Texas Instrum. (India) Ltd., Bangalore, India
S.U. Hegde , Texas Instrum. (India) Ltd., Bangalore, India
I.P. Pal , Texas Instrum. (India) Ltd., Bangalore, India
pp. 50
Low Power

A low-power high storage capacity structure for GaAs MESFET ROM (Abstract)

A. Guyot , Electron. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland
R. Kanan , Electron. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland
M. Declercq , Electron. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland
B. Hochet , Electron. Lab., Swiss Federal Inst. of Technol., Lausanne, Switzerland
pp. 58

Use of selective precharge for low-power on the match lines of content-addressable memories (Abstract)

C.A. Zukowski , Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
Shao-Yi Wang , Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
pp. 64
Test

An open notation for memory tests (Abstract)

A.J. van de Goor , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
A. Offerman , Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 71

Testing memory modules in SRAM-based configurable FPGAs (Abstract)

F. Lombardi , Dept. of Electr. Eng., Fudan Univ., Shanghai, China
W.K. Huang , Dept. of Electr. Eng., Fudan Univ., Shanghai, China
F.J. Meyer , Dept. of Electr. Eng., Fudan Univ., Shanghai, China
N. Park , Dept. of Electr. Eng., Fudan Univ., Shanghai, China
pp. 79

Memory array testing through a scannable configuration (Abstract)

N. Ishiura , 1st Comput. Oper. Unit, NEC Corp., Tokyo, Japan
S. Yano , 1st Comput. Oper. Unit, NEC Corp., Tokyo, Japan
pp. 87
Sensing

A high-speed parallel sensing scheme for multi-level non-volatile memories (Abstract)

C. Calligaro , Dipt. di Elettronica, Pavia Univ., Italy
R. Gastaldi , Dipt. di Elettronica, Pavia Univ., Italy
G. Torelli , Dipt. di Elettronica, Pavia Univ., Italy
A. Manstretta , Dipt. di Elettronica, Pavia Univ., Italy
pp. 96

Index of Authors (PDF)

pp. 103
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