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Microelectronics Systems Education, IEEE International Conference on (1997)
Arlington, VA
July 21, 1997 to July 23, 1997
ISBN: 0-8186-7996-4
pp: 0016
Roberto Giorgi , Dipartimento di Ingegneria della Informazione Universita` di Pisa - Italy
Cosimo Antonio Prete , Dipartimento di Ingegneria della Informazione Universita` di Pisa - Italy
Gianpaolo Prina , Dipartimento di Ingegneria della Informazione Universita` di Pisa - Italy
ABSTRACT
Cache memory design in embedded systems can take advantage from the analysis of the software that runs on that system, which usually remains the same for its whole life. Programs can be characterized, in respect of the memory hierarchy, using locality analysis. We propose an environment which permits to analyze the locality of a program and the effects on the target system performance. The student can thus figure out the best tradeoff between costs and performance for cache, memory and timings exploring different system configurations. A fully graphical interface permits to observe the program behavior from many points of view: locality surface, working set evolution, performance metrics. The tool is currently used as a teaching tool at our University and it is distributed as part of a commercial development environment for embedded systems.
INDEX TERMS
Embedded System, Program Locality, Cache, Didactic Tool, Performance Evaluation
CITATION
Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, "Cache Memory Design for Embedded Systems Based on Program Locality Analysis", Microelectronics Systems Education, IEEE International Conference on, vol. 00, no. , pp. 0016, 1997, doi:10.1109/MSE.1997.612528
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