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Microelectronics for Neural Networks and Fuzzy Systems, International Conference on/Microelectronics for Neural, Fuzzy, and Bio-Inspired Systems, International Conference on (1996)
Lausanne, SWITZERLAND
Feb. 12, 1996 to Feb. 14, 1996
ISSN: 1086-1947
ISBN: 0-8186-7373-7
TABLE OF CONTENTS

Foreword (PDF)

pp. ix
Session 1 -- Vision: Chair: E. Vittoz - Neuch?tel

Retinomorphic Vision System (Abstract)

Kwabena Boahen , Physics of Computation Laboratory California Institute of Technology
pp. 2
Session 2 -- Bio-Inspiration: Chair: L. Reyneri - Torino

An Hindmarsh and Rose Based Electronic Burster (Abstract)

N. Silvestre , Theoretical Physics Group French German Research Institute of Saint-Louis
L. Merlat , Theoretical Physics Group French German Research Institute of Saint-Louis
pp. 39

Analog VLSI System for Active Drag Reduction (Abstract)

Bhusan Gupta , Dept. of Electrical Engineering California Institute of Technology Pasadena, CA 91125
Fukang Jiang , Dept. of Electrical Engineering California Institute of Technology Pasadena, CA 91125
Rodney Goodman , Dept. of Electrical Engineering California Institute of Technology Pasadena, CA 91125
Yu-Chong Tai , Dept. of Electrical Engineering California Institute of Technology Pasadena, CA 91125
Chih-Ming Ho , MANE, UCLA
Steve Tung , MANE, UCLA
pp. 45

An Analogue Electronic Model of Ventral Cochlear Nucleus Neurons (Abstract)

Eric Vittoz , Mantra Centre for Neuromimetic Systems Swiss Federal Institute of Technology
Andre Van Schaik , Mantra Centre for Neuromimetic Systems Swiss Federal Institute of Technology
Eric Fragnière , Mantra Centre for Neuromimetic Systems Swiss Federal Institute of Technology
pp. 52
Session 3 -- Analog Implementations: Chair: X. Arreguit - Neuch?tel

Array-based analog computation: principles, advantages and limitations (Abstract)

A.H. Kramer , Neural Network Design Group, SGS-Thomson Microelectron., Milan, Italy
pp. 68

Low-power analog fuzzy rule implementation based on a linear MOS transistor network (Abstract)

O. Landolt , Centre Suisse d'Electronique et de Microtechnique SA, Neuchatel, Switzerland
pp. 86

Neuron-MOS-based association hardware for real-time event recognition (Abstract)

T. Nakai , Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan
M. Konda , Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan
T. Ohmi , Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan
T. Shibata , Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan
Y. Yamashita , Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan
pp. 94
Session 4 -- Analog for Image Processing: Chair: A. Prieto - Granada

Current Mode CMOS Multi Layer Perceptron Chip (Abstract)

D.D. Caviglia , DIBE - University of Genoa, Italy
G.M. Bo , DIBE - University of Genoa, Italy
M. Valle , DIBE - University of Genoa, Italy
pp. 103

Low power, low voltage conductance-mode CMOS analog neuron (Abstract)

A. Kramer , Neural Network Design Group, SGS-Thomson Microelectron., Milan, Italy
V. Fabbrizio , Neural Network Design Group, SGS-Thomson Microelectron., Milan, Italy
G. Colli , Neural Network Design Group, SGS-Thomson Microelectron., Milan, Italy
X. Mariaud , Neural Network Design Group, SGS-Thomson Microelectron., Milan, Italy
F. Raynal , Neural Network Design Group, SGS-Thomson Microelectron., Milan, Italy
pp. 111
Session 5 -- Learning, Innovations: Chair: K. Goser - Dortmund

Simulated Annealing of Binary Fields Using an Optoelectronic Circuit (Abstract)

Jean-Claude Rodier , Universit? de Paris
Philipe Lalanne , Universit? de Paris
Patrick Gardax , Universit? de Paris
Donald Prevost , Universit? de Paris
Antoine Dupret , Universit? de Paris
Pierre Chavel , Universit? de Paris
Eric Belhaire , Universit? de Paris
pp. 131
Session 6 -- Digital Implementations: Chair: U. Ramacher - Dresden

A Digital Neural Network LSI Using Sparse Memory Access Architecture (Abstract)

Kuniharu Uchimura , NTT LSI Laboratories
Osamu Fujita , NTT LSI Laboratories
Kimihisa Aihara , NTT LSI Laboratories
pp. 139

On-Chip Backpropagation Training Using Parallel Stochastic Bit Streams (Abstract)

Karl-Ragmar Riemschneider , Universitt der Bundeswehr Hamburg
Hans Christoph Zeidler , Universitt der Bundeswehr Hamburg
Kuno Köllmann , Universitt der Bundeswehr Hamburg
pp. 149

A CMAC-Type Neural Memory for Control Applications (Abstract)

W. S. Mischo , Control Systems Theory and Robotics Group Technische Hochschule Darmstadt
pp. 161

On-line arithmetic-based reprogrammable hardware implementation of multilayer perceptron back-propagation (Abstract)

B. Girau , Lab. d'Inf. du Parallelisme, CNRS, Lyon, France
A. Tisserand , Lab. d'Inf. du Parallelisme, CNRS, Lyon, France
pp. 168
Session 7 -- Pulse Stream Networks: Chair: D. Del Corso - Torino

A low-power Neuro-Fuzzy pulse stream system (Abstract)

L.M. Reyneri , Dipartimento di Elettronica, Politecnico di Torino, Italy
E. Miranda Sologuren , Dipartimento di Elettronica, Politecnico di Torino, Italy
M. Chiaberge , Dipartimento di Elettronica, Politecnico di Torino, Italy
pp. 191
Session 8 -- Systems: Chair: H.P. Graf - Holmdel

On-Line Hand-Printing Recognition with Neural Networks (Abstract)

Richard F. Lyon , Apple Computer, Inc.
Larry S. Yaeger , Apple Computer, Inc.
pp. 201

Design of a Low-Cost and High-Speed Neurocomputer System (Abstract)

Ramon Capillas , Departemento de Diseno de CIs Universidad Autonoma de Barcelona - C.N.M.
J. Alberto Fernandez , Departemento de Diseno de CIs Universidad Autonoma de Barcelona - C.N.M.
Elena Valderrama , Departemento de Diseno de CIs Universidad Autonoma de Barcelona - C.N.M.
Narcis Avellana , Abteilung Allgemeine Elektrotechnik und Mikroelektronik Universitaet Ulm
Alfred Strey , Abteilung Neuroinformatik Universitaet Ulm
Raul Holgado , Departemento de Diseno de CIs Universidad Autonoma de Barcelona - C.N.M.
pp. 221

SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training (Abstract)

Krste Asanovic , University of California at Berkeley
Brian Kingsbury , University of California at Berkeley
John Wawrzynek , University of California at Berkeley
David Johnson , International Computer Science Institute
James Beck , International Computer Science Institute
Nelson Morgan , International Computer Science Institute
pp. 227
Poster Session

Adaptive two-dimensional neuron grids (Abstract)

A. Kronig , Dept. of Electr. Eng., Tech. Univ. Dresden, Germany
U. Ramacher , Dept. of Electr. Eng., Tech. Univ. Dresden, Germany
pp. 246

A correlation-based network for hardware implementations (Abstract)

J. Ngole , Dept. of Comput. Sci., Uppsala Univ., Sweden
L. Asplund , Dept. of Comput. Sci., Uppsala Univ., Sweden
pp. 251

Direct Synthesis of Neural Networks (Abstract)

John G. Taylor , Centre for Neural Networks, Department of Mathematics King's College London, Strand, London WC2R 2LS, United Kingdom
Valeriu Beiu , Centre for Neural Networks, Department of Mathematics King's College London, Strand, London WC2R 2LS, United Kingdom
pp. 257

A modified RBF neural network for efficient current-mode VLSI implementation (Abstract)

R. Dogaru , Dept. of Appl. Electron., Politehnic Inst. of Bucharest, Romania
A.T. Murgan , Dept. of Appl. Electron., Politehnic Inst. of Bucharest, Romania
S. Ortmann , Dept. of Appl. Electron., Politehnic Inst. of Bucharest, Romania
M. Glesner , Dept. of Appl. Electron., Politehnic Inst. of Bucharest, Romania
pp. 265

An Analog Floating-gate Memory in a Standard Digital Technology (Abstract)

Tor Sverre Lande , University of Oslo Blindern N-0316 Oslo, NORWAY
pp. 271

A Scalable Processor Array for Self-Organizing Feature Maps (Abstract)

U. Rückert , Heinz Nixdorf Institut Universitaet GH Paderborn
S. Rüping , Heinz Nixdorf Institut Universitaet GH Paderborn
pp. 285

A low-power high-precision tunable WINNER-TAKE-ALL network (Abstract)

R. Canegallo , Neural Network Design Group, SGS-Thomson Microelectron., Agrate Brianza, Italy
A. Kramer , Neural Network Design Group, SGS-Thomson Microelectron., Agrate Brianza, Italy
M. Chinosi , Neural Network Design Group, SGS-Thomson Microelectron., Agrate Brianza, Italy
pp. 292

Computational Image Sensors for On-Sensor-Compression (Abstract)

M. Hatori , The University of Tokyo
Y. Egi , The University of Tokyo
K. Aizawa , The University of Tokyo
T. Hamamoto , The University of Tokyo
pp. 297

A CMOS implementation of fuzzy controllers based on adaptive membership function ranges (Abstract)

I. Rojas , Dept. de Electron. y Tecnologia de Computadores, Granada Univ., Spain
F.J. Pelayo , Dept. de Electron. y Tecnologia de Computadores, Granada Univ., Spain
O. Ortega , Dept. de Electron. y Tecnologia de Computadores, Granada Univ., Spain
A. Prieto , Dept. de Electron. y Tecnologia de Computadores, Granada Univ., Spain
pp. 317

VIP: An FPGA-based Processor for Image Processing and Neural Networks (Abstract)

Steven Pigeon , Universite de Montreal
Patrice Y. Simard , AT&T Bell Laboratories
Eric Cosatto , AT&T Bell Laboratories
Jocelyn Cloutier , Universite de Montreal
Francois R. Boyer , Universite de Montreal
pp. 330

The FAST Architecture: A Neural Network with Flexible Adaptable-Size Topology (Abstract)

Eduardo Sanchez , Logic Systems Laboratory Swiss Federal Institute of Technology
Andres Pérez , Logic Systems Laboratory Swiss Federal Institute of Technology
pp. 337

A Variable-Precision Systolic Architecture for ANN Computation (Abstract)

A. Bermak , LAAS/CNRS 7, Ave du colonnel Roche
D. Martinez , LAAS/CNRS 7, Ave du colonnel Roche
pp. 347

Author Index (PDF)

pp. 369
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