Microelectronics for Neural Networks and Fuzzy Systems, International Conference on/Microelectronics for Neural, Fuzzy, and Bio-Inspired Systems, International Conference on (1996)
Feb. 12, 1996 to Feb. 14, 1996
Jocelyn Cloutier , Universite de Montreal
Steven Pigeon , Universite de Montreal
Francois R. Boyer , Universite de Montreal
Eric Cosatto , AT&T Bell Laboratories
Patrice Y. Simard , AT&T Bell Laboratories
We present in this paper the architecture and implementation of the Virtual Image Processor (VIP) which is an SIMD multiprocessor build with large FPGAs. The SIMD architecture , together with a 2D torus connection topology, is well suited for image processing, pattern recognition and neural network algorithms. The VIP board can be programmed on-line at the logic level, allowing optimal hardware dedication to any given algorithm.
S. Pigeon, P. Y. Simard, E. Cosatto, J. Cloutier and F. R. Boyer, "VIP: An FPGA-based Processor for Image Processing and Neural Networks," Microelectronics for Neural Networks and Fuzzy Systems, International Conference on/Microelectronics for Neural, Fuzzy, and Bio-Inspired Systems, International Conference on(MICRONEURO), Lausanne, SWITZERLAND, 1996, pp. 330.