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2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (2008)
Como, Italy
Nov. 8, 2008 to Nov. 12, 2008
ISBN: 978-1-4244-2836-6
TABLE OF CONTENTS
Papers

Table of contents (PDF)

pp. viii-xi

[Front cover] (PDF)

pp. c1

Referees (PDF)

pp. vi-vii

Referees (PDF)

pp. vi-vii
Papers

Temporal instruction fetch streaming (Abstract)

Michael Ferdman , Computer Architecture Lab (CALCM), Carnegie Mellon University, Pittsburgh, PA, USA
Thomas F. Wenisch , Advanced Computer Architecture Lab (ACAL), University of Michigan, Ann Arbor, USA
Anastasia Ailamaki , Computer Architecture Lab (CALCM), Carnegie Mellon University, Pittsburgh, PA, USA
Andreas Moshovos , Department of ECE, University of Toronto, Canada
Babak Falsafi , Parallel Systems Architecture Lab (PARSA), Ecole Polytechnique F
pp. 1-10

A distributed processor state management architecture for large-window processors (Abstract)

Alex Veidenbaum , Department of Computer Science, UC Irvine, USA
Adrian Cristal , Department of Computer Architecture, BSC - CNS, Barcelona, Spain
Marco Galluzzi , Department of Computer Architecture, UPC, Barcelona, Spain
Mateo Valero , Department of Computer Architecture, UPC, Barcelona, Spain
Marco A. Ramirez , Center for Computing Research, IPN, M
Isidro Gonzalez , Department of Computer Architecture, UPC, Barcelona, Spain
pp. 11-22

Strategies for mapping dataflow blocks to distributed hardware (Abstract)

Doug Burger , Microsoft Rsearch, One Microsoft Way Redmond, WA 98052, USA
Behnam Robatmili , Department of Computer Sciences, The University of Texas at Austin, USA
Katherine E. Coons , Department of Computer Sciences, The University of Texas at Austin, USA
Kathryn S. McKinley , Department of Computer Sciences, The University of Texas at Austin, USA
pp. 23-34

Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence (Abstract)

Li-Shiuan Peh , Dept of Electrical Engineering, Princeton University, NJ 08544, USA
Natalie D. Enright Jerger , Dept of Electrical and Comp. Engineering, University of Wisconsin-Madison, 53706, USA
Mikko H. Lipasti , Dept of Electrical and Comp. Engineering, University of Wisconsin-Madison, 53706, USA
pp. 35-46

Token tenure: PATCHing token counting using directory-based cache coherence (Abstract)

Colin Blundell , Department of Computer and Information Science, University of Pennsylvania, Philadelphia, USA
Milo M. K. Martin , Department of Computer and Information Science, University of Pennsylvania, Philadelphia, USA
Arun Raghavan , Department of Computer and Information Science, University of Pennsylvania, Philadelphia, USA
pp. 47-58

Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs (Abstract)

Xi E. Chen , Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, CANADA
Tor M. Aamodt , Department of Electrical and Computer Engineering, University of British Columbia, Vancouver, CANADA
pp. 59-70

Implementing high availability memory with a duplication cache (Abstract)

James E. Smith , University of Wisconsin-Madison, USA
Parthasarathy Ranganathan , Hewlett Packard Labs, Palo Alto, California, USA
Norman P. Jouppi , Hewlett Packard Labs, Palo Alto, California, USA
Kewal K. Saluja , University of Wisconsin-Madison, USA
Nidhi Aggarwal , University of Wisconsin-Madison, USA
pp. 71-82

A novel cache architecture with enhanced performance and security (Abstract)

Zhenghong Wang , Princeton Architecture Laboratory for Multimedia and Security (PALMS), Department of Electrical Engineering, Princeton University, NJ 08544, USA
Ruby B. Lee , Princeton Architecture Laboratory for Multimedia and Security (PALMS), Department of Electrical Engineering, Princeton University, NJ 08544, USA
pp. 83-93

A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags (Abstract)

Shashidhar Mysore , Department of Computer Science, University of California, Santa Barbara, USA
Jonathan Valamehr , Department of Electrical and Computer Engineering, University of California, Santa Barbara, USA
Banit Agrawal , Department of Computer Science, University of California, Santa Barbara, USA
Timothy Sherwood , Department of Computer Science, University of California, Santa Barbara, USA
Mohit Tiwari , Department of Computer Science, University of California, Santa Barbara, USA
pp. 94-105

SHARK: Architectural support for autonomic protection against stealth by rootkit exploits (Abstract)

Hsien-Hsin S. Lee , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332, USA
Vikas R. Vasisht , School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, 30332, USA
pp. 106-116

Testudo: Heavyweight security analysis via statistical sampling (Abstract)

Valeria Bertacco , Advanced Computer Architecture Lab, University of Michigan, Ann Arbor, USA
Joseph L. Greathouse , Advanced Computer Architecture Lab, University of Michigan, Ann Arbor, USA
Gautam Bhatnagar , Advanced Computer Architecture Lab, University of Michigan, Ann Arbor, USA
Todd Austin , Advanced Computer Architecture Lab, University of Michigan, Ann Arbor, USA
Ilya Wagner , Advanced Computer Architecture Lab, University of Michigan, Ann Arbor, USA
Seth Pettie , Advanced Computer Architecture Lab, University of Michigan, Ann Arbor, USA
David A. Ramos , Advanced Computer Architecture Lab, University of Michigan, Ann Arbor, USA
pp. 117-128

Facelift: Hiding and slowing down aging in multicores (Abstract)

Josep Torrellas , Department of Computer Science, University of Illinois at Urbana-Champaign, USA
Abhishek Tiwari , Department of Computer Science, University of Illinois at Urbana-Champaign, USA
pp. 129-140

The StageNet fabric for constructing resilient multicore systems (Abstract)

Shantanu Gupta , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109, USA
Amin Ansari , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109, USA
Jason Blome , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109, USA
Shuguang Feng , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109, USA
Scott Mahlke , Advanced Computer Architecture Laboratory, University of Michigan, Ann Arbor, 48109, USA
pp. 141-151

From SODA to scotch: The evolution of a wireless baseband processor (Abstract)

Trevor Mudge , Advanced Computer Architecture Laboratory, University of Michigan - Ann Arbor, USA
Scott Mahlke , Advanced Computer Architecture Laboratory, University of Michigan - Ann Arbor, USA
Yuan Lin , Advanced Computer Architecture Laboratory, University of Michigan - Ann Arbor, USA
Sangwon Seo , Advanced Computer Architecture Laboratory, University of Michigan - Ann Arbor, USA
Mladen Wilder , ARM, Ltd., Cambridge, United Kingdom
Chaitali Chakrabarti , Department of Electrical Engineering, Arizona State University, Tempe, USA
Krisztian Flautner , ARM, Ltd., Cambridge, United Kingdom
Mark Woh , Advanced Computer Architecture Laboratory, University of Michigan - Ann Arbor, USA
Alastair Reid , ARM, Ltd., Cambridge, United Kingdom
Danny Kershaw , ARM, Ltd., Cambridge, United Kingdom
Richard Bruce , ARM, Ltd., Cambridge, United Kingdom
pp. 152-163

Tradeoffs in designing accelerator architectures for visual computing (Abstract)

Daniel Johnson , Center for Reliable and High-Performance Computing, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, USA
Neal Crago , Center for Reliable and High-Performance Computing, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, USA
Sanjay J. Patel , Center for Reliable and High-Performance Computing, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, USA
Aqeel Mahesri , Center for Reliable and High-Performance Computing, Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, USA
pp. 164-175

Toward a multicore architecture for real-time ray-tracing (Abstract)

Mary Vernon , Department of Computer Sciences, University of Wisconsin-Madison, USA
Peter Djeu , Department of Computer Sciences, The University of Texas at Austin, USA
Karthikeyan Sankaralingam , Department of Computer Sciences, University of Wisconsin-Madison, USA
Venkatraman Govindaraju , Department of Computer Sciences, University of Wisconsin-Madison, USA
William R. Mark , Department of Computer Sciences, The University of Texas at Austin, USA
pp. 176-187

Power to the people: Leveraging human physiological traits to control microprocessor frequency (Abstract)

Yan Pan , Department of Electrical Engineering and Computer Science, Northwestern University, Evanston IL, USA
J. Scott Miller , Department of Electrical Engineering and Computer Science, Northwestern University, Evanston IL, USA
Ben Scholbrock , Department of Electrical Engineering and Computer Science, Northwestern University, Evanston IL, USA
Peter A. Dinda , Department of Electrical Engineering and Computer Science, Northwestern University, Evanston IL, USA
Robert P. Dick , Department of Electrical Engineering and Computer Science, Northwestern University, Evanston IL, USA
Alex Shye , Department of Electrical Engineering and Computer Science, Northwestern University, Evanston IL, USA
Gokhan Memik , Department of Electrical Engineering and Computer Science, Northwestern University, Evanston IL, USA
pp. 188-199

Prefetch-Aware DRAM Controllers (Abstract)

Chang Joo Lee , Department of Electrical and Computer Engineering, The University of Texas at Austin, USA
Onur Mutlu , Microsoft Research and Carnegie Mellon University, USA
Veynu Narasiman , Department of Electrical and Computer Engineering, The University of Texas at Austin, USA
Yale N. Patt , Department of Electrical and Computer Engineering, The University of Texas at Austin, USA
pp. 200-209

Mini-rank: Adaptive DRAM architecture for improving memory power efficiency (Abstract)

Hongzhong Zheng , Department of Electrical and Computer Engineering, University of Illinois at Chicago, USA
Jiang Lin , Department of Electrical and Computer Engineering, Iowa State University, USA
Eugene Gorbatov , Corporate Technology Group, Intel Corp., Hillsboro, OR 9712, USA
Zhichun Zhu , Department of Electrical and Computer Engineering, University of Illinois at Chicago, USA
Zhao Zhang , Department of Electrical and Computer Engineering, Iowa State University, USA
Howard David , Corporate Technology Group, Intel Corp., Hillsboro, OR 9712, USA
pp. 210-221

Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency (Abstract)

Doug Burger , Microsoft Research, One Microsoft Way Redmond, WA, USA
Michael Ferdman , Dept. of Elec.&Comp. Eng., Carnegie Mellon University, USA
Jaehyuk Huh , Advanced Micro Devices, USA
Haiming Liu , Dept. of Computer Sciences, The University of Texas at Austin, USA
pp. 222-233

Notary: Hardware techniques to enhance signatures (Abstract)

Mark D. Hill , Department of Computer Sciences, University of Wisconsin-Madison, U.S.A.
Stark C. Draper , Department of Electrical and Computer Engineering, University of Wisconsin-Madison, U.S.A.
Luke Yen , Department of Computer Sciences, University of Wisconsin-Madison, U.S.A.
pp. 234-245

Dependence-aware transactional memory for increased concurrency (Abstract)

Emmett Witchel , Department of Computer Sciences, University of Texas at Austin, USA
Christopher J. Rossbach , Department of Computer Sciences, University of Texas at Austin, USA
Hany E. Ramadan , Department of Computer Sciences, University of Texas at Austin, USA
pp. 246-257

Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer (Abstract)

Michael Stumm , Department of Electrical and Computer Engineering, University of Toronto, Canada
David Tam , Department of Electrical and Computer Engineering, University of Toronto, Canada
Livio Soares , Department of Electrical and Computer Engineering, University of Toronto, Canada
pp. 258-269

CPR: Composable performance regression for scalable multiprocessor models (Abstract)

Hong Wang , Intel Corporation, USA
Benjamin C. Lee , Microsoft Research, USA
David Brooks , Harvard University, USA
Jamison Collins , Intel Corporation, USA
pp. 270-281

Online design bug detection: RTL analysis, flexible mechanisms, and evaluation (Abstract)

Todd Austin , Advanced Computer Architecture Lab, University of Michigan, USA
Kypros Constantinides , Advanced Computer Architecture Lab, University of Michigan, USA
Onur Mutlu , Microsoft Research and Carnegie Mellon University, USA
pp. 282-293

Verification of chip multiprocessor memory systems using a relaxed scoreboard (Abstract)

Alex Solomatnikov , Department of Electrical Engineering, Stanford University, California, USA
Megan Wachs , Department of Electrical Engineering, Stanford University, California, USA
Amin Firoozshahian , Department of Electrical Engineering, Stanford University, California, USA
Mark Horowitz , Department of Electrical Engineering, Stanford University, California, USA
Stephen Richardson , Department of Electrical Engineering, Stanford University, California, USA
Ofer Shacham , Department of Electrical Engineering, Stanford University, California, USA
pp. 294-305

A performance-correctness explicitly-decoupled architecture (Abstract)

Michael C. Huang , Department of Electrical&Computer Engineering, University of Rochester, USA
Alok Garg , Department of Electrical&Computer Engineering, University of Rochester, USA
pp. 306-317

Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approach (Abstract)

Ramazan Bitirgen , Computer Systems Laboratory, Cornell University, Ithaca, NY 14853 USA
Jose F. Martinez , Computer Systems Laboratory, Cornell University, Ithaca, NY 14853 USA
Engin Ipek , Microsoft Research, Redmond, WA 98052 USA
pp. 318-329

Copy or Discard execution model for speculative parallelization on multicores (Abstract)

Min Feng , Department of Computer Science and Engineering, University of California at Riverside, U.S.A
Vijay Nagarajan , Department of Computer Science and Engineering, University of California at Riverside, U.S.A
Rajiv Gupta , Department of Computer Science and Engineering, University of California at Riverside, U.S.A
Chen Tian , Department of Computer Science and Engineering, University of California at Riverside, U.S.A
pp. 330-341

Token flow control (Abstract)

Amit Kumar , Department of Electrical Engineering, Princeton University, NJ 08544, USA
Niraj K. Jha , Department of Electrical Engineering, Princeton University, NJ 08544, USA
Li-Shiuan Peh , Department of Electrical Engineering, Princeton University, NJ 08544, USA
pp. 342-353

Adaptive data compression for high-performance low-power on-chip networks (Abstract)

Ki Hwan Yum , Department of Computer Science, University of Texas at San Antonio, 78249 USA
Eun Jung Kim , Department of Computer Science, Texas A&M University, College Station, 77843 USA
Yuho Jin , Department of Computer Science, Texas A&M University, College Station, 77843 USA
pp. 354-363

Efficient unicast and multicast support for CMPs (Abstract)

Samuel Rodrigo , Parallel Architectures Group, Technical University of Valencia, Spain
Jose Duato , Parallel Architectures Group, Technical University of Valencia, Spain
Jose Flich , Parallel Architectures Group, Technical University of Valencia, Spain
Mark Hummel , AMD, USA
pp. 364-375

Power reduction of CMP communication networks via RF-interconnects (Abstract)

Glenn Reinman , Computer Science Department, UCLA, USA
Eran Socher , Electrical Engineering Department, UCLA, USA
Chunyue Liu , Computer Science Department, UCLA, USA
Jagannath Premkumar , Computer Science Department, UCLA, USA
Mishali Naik , Computer Science Department, UCLA, USA
Sai-Wang Tam , Electrical Engineering Department, UCLA, USA
Adam Kaplan , Computer Science Department, UCLA, USA
Jason Cong , Computer Science Department, UCLA, USA
M-C. Frank Chang , Electrical Engineering Department, UCLA, USA
pp. 376-387

Evaluating the effects of cache redundancy on profit (Abstract)

Berkin Ozisikyilmaz , Electrical Engineering and Computer Science Department, Northwestern University, Evanston, IL USA
Abhishek Das , Electrical Engineering and Computer Science Department, Northwestern University, Evanston, IL USA
Joseph Zambreno , Electrical and Computer Engineering Department, Iowa State University, Ames, USA
Serkan Ozdemir , Electrical Engineering and Computer Science Department, Northwestern University, Evanston, IL USA
Gokhan Memik , Electrical Engineering and Computer Science Department, Northwestern University, Evanston, IL USA
Alok Choudhary , Electrical Engineering and Computer Science Department, Northwestern University, Evanston, IL USA
pp. 388-398

NBTI tolerant microarchitecture design in the presence of process variation (Abstract)

Xin Fu , Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA, 32611
Jose Fortes , Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA, 32611
Tao Li , Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA, 32611
pp. 399-410

Shapeshifter: Dynamically changing pipeline width and speed to address process variations (Abstract)

Eric Chun , Intel Corporation, Austin, Texas, USA
T. N. Vijaykumar , Purdue University, West Lafayette, Indiana, USA
Zeshan Chishti , Intel Corporation, Austin, Texas, USA
pp. 411-422

EVAL: Utilizing processors with variation-induced timing errors (Abstract)

Smruti Sarangi , Department of Computer Science, University of Illinois at Urbana-Champaign, USA
Abhishek Tiwari , Department of Computer Science, University of Illinois at Urbana-Champaign, USA
Brian Greskamp , Department of Computer Science, University of Illinois at Urbana-Champaign, USA
Josep Torrellas , Department of Computer Science, University of Illinois at Urbana-Champaign, USA
pp. 423-434

Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technology (Abstract)

Wangyuan Zhang , Intelligent Design of Efficient Architecture Lab (IDEAL), Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA, 32611
Tao Li , Intelligent Design of Efficient Architecture Lab (IDEAL), Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA, 32611
pp. 435-446

Low-power, high-performance analog neural branch prediction (Abstract)

Daniel A. Jimenez , Department of Computer Science, The University of Texas at San Antonio, USA
Doug Burger , Microsoft Research, One Microsoft Way, Redmond, WA 98052, USA
Renee St. Amant , Department of Computer Sciences, The University of Texas at Austin, USA
pp. 447-458

Reconfigurable energy efficient near threshold cache architectures (Abstract)

Trevor Mudge , University of Michigan - Ann Arbor, USA
David Blaauw , University of Michigan - Ann Arbor, USA
Dennis Sylvester , University of Michigan - Ann Arbor, USA
Gregory K. Chen , University of Michigan - Ann Arbor, USA
Krisztian Flautner , ARM, Ltd., Cambridge, United Kingdom
Ronald G. Dreslinski , University of Michigan - Ann Arbor, USA
pp. 459-470

Author index (PDF)

pp. 471-472
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