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40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007) (2007)
Chicago, Illinois, USA
Dec. 1, 2007 to Dec. 5, 2007
ISSN: 1072-4451
ISBN: 0-7695-3047-8
pp: 381-394
ABSTRACT
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within pro- cessors and thread-level parallelism (TLP) within and across processors. However, the number of processors and the granularity of each processor are fixed at de- sign time. This paper evaluates a flexible architectural approach, called Composable Lightweight Processors (or CLPs), that allows simple, low-power cores to be aggre- gated together dynamically, forming larger, more powerful single-threaded processors without changing the applica- tion binary. We evaluate one such design with 32 cores called TFlex, which can be configured as 32 dual-issue pro- cessors, or as a single 64-wide issue processor, or as any point in between. Use of an Explicit Data Graph Execution (EDGE) ISA enables the system to be fully composable, with no monolithic structures spanning the cores. Simulation re- sults show that CLPs achieve an average performance boost of 42%, an average area-efficiency of 3.4x, and an average power-efficiency of 2x over a fixed architecture on a spec- trum of single-threaded applications. Results also show that CLPs outperform a spectrum of fixed CMP architectures on a set of multitasking workloads.
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CITATION

D. Gulati et al., "Composable Lightweight Processors," 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)(MICRO), Chicago, Illinois, USA, 2007, pp. 381-394.
doi:10.1109/MICRO.2007.41
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