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2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (2006)
Orlando, Florida, USA
Dec. 9, 2006 to Dec. 13, 2006
ISSN: 1072-4451
ISBN: 0-7695-2732-9
TABLE OF CONTENTS

Reviewers (PDF)

pp. xii
Introduction
Introduction

Reviewers (PDF)

pp. xii

Sponsors (PDF)

pp. xiv
Session 1: Reliability and Bug Detection

A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design (Abstract)

Michael B. Healy , Georgia Institute of Technology, USA
Fayez Mohamood , Georgia Institute of Technology, USA
Hsien-Hsin S. Lee , Georgia Institute of Technology, USA
Sung Kyu Lim , Georgia Institute of Technology, USA
pp. 3-14

Yield-Aware Cache Architectures (Abstract)

Serkan Ozdemir , Northwestern University
Gokhan Memik , Northwestern University
Jonathan Adams , Northwestern University
Hai Zhou , Northwestern University
Debjit Sinha , Northwestern University; IBM Microelectronics, USA
pp. 15-25

Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware (Abstract)

Josep Torrellas , University of Illinois at Urbana-Champaign, USA
Abhishek Tiwari , University of Illinois at Urbana-Champaign, USA
Smruti R. Sarangi , University of Illinois at Urbana-Champaign, USA
pp. 26-37

PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection (Abstract)

Josep Torrellas , University of Illinois at Urbana Champaign, USA
Wei Liu , University of Illinois at Urbana Champaign, USA
Shan Lu , University of Illinois at Urbana Champaign, USA
Yuanyuan Zhou , University of Illinois at Urbana Champaign, USA
Pin Zhou , University of Illinois at Urbana Champaign, USA
pp. 38-52
Session 2A: Compiler and Branch Handling

Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths (Abstract)

Onur Mutlu , Microsoft Research
Hyesoon Kim , University of Texas at Austin
Yale N. Patt , University of Texas at Austin
Jose A. Joao , University of Texas at Austin
pp. 53-64

Merging Head and Tail Duplication for Convergent Hyperblock Formation (Abstract)

Kathryn S. McKinley , University of Texas at Austin
Bertrand A. Maher , University of Texas at Austin
Aaron Smith , University of Texas at Austin
Doug Burger , University of Texas at Austin
pp. 65-76

Data-Dependency Graph Transformations for Superblock Scheduling (Abstract)

Kent Wilken , University of California, Davis
Mark Heffernan , University of California, Davis
Ghassan Shobaki , University of California, Davis
pp. 77-88

Dataflow Predication (Abstract)

Ramadass Nagarajan , University of Texas at Austin
Kathryn S. McKinley , University of Texas at Austin
Karthikeyan Sankaralingam , University of Texas at Austin
Robert McDonald , University of Texas at Austin
Aaron Smith , University of Texas at Austin
Doug Burger , University of Texas at Austin
Stephen W. Keckler , University of Texas at Austin
pp. 89-102
Session 2B: Security

Authentication Control Point and Its Implications For Secure Processor Design (Abstract)

Hsien?Hsin S. Lee , Georgia Institute of Technology
Weidong Shi , Motorola, Inc.
pp. 103-112

Using Branch Correlation to Identify Infeasible Paths for Anomaly Detection (Abstract)

Santosh Pande , Georgia Institute of Technology
Xiaotong Zhuang , IBM T.J. Watson Research Center, NY
Tao Zhang , IBM T.J. Watson Research Center, NY
pp. 113-122

Memory Protection through Dynamic Access Control (Abstract)

Santosh Pande , Georgia Institute of Technology
Tao Zhang , Georgia Institute of Technology
Kun Zhang , Georgia Institute of Technology
pp. 123-134

LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks (Abstract)

Youfeng Wu , Intel Corporation
Cheng Wang , Intel Corporation
Feng Qin , Ohio State University
Zhenmin Li , University of Illinois at Urbana-Champaign
Ho-seop Kim , Intel Corporation
Yuanyuan Zhou , University of Illinois at Urbana-Champaign
pp. 135-148
Session 3A: Superscalar Processors

Fairness and Throughput in Switch on Event Multithreading (Abstract)

Avi Mendelson , Intel, Israel
Ron Gabor , Tel Aviv University, Israel
Shlomo Weiss , Tel Aviv University, Israel
pp. 149-160
Session 3A: Superscalar Processors

Serialization-Aware Mini-Graphs: Performance with Fewer Resources (Abstract)

Amir Roth , University of Pennsylvania
Anne Bracy , University of Pennsylvania
pp. 171-184
Session 3B: Memory Systems

Architectural Support for Software Transactional Memory (Abstract)

Ali-Reza Adl-Tabatabai , Microprocessor Technology Lab, Intel Corporation
Bratin Saha , Microprocessor Technology Lab, Intel Corporation
Quinn Jacobson , Microprocessor Technology Lab, Intel Corporation
pp. 185-196

Virtually Pipelined Network Memory (Abstract)

Banit Agrawal , University of California, Santa Barbara
Timothy Sherwood , University of California, Santa Barbara
pp. 197-207

Fair Queuing Memory Systems (Abstract)

James Laudon , Sun Microsystems, Inc.
James E. Smith , University of Wisconsin, Madison
Nidhi Aggarwal , University of Wisconsin, Madison
Kyle J. Nesbit , University of Wisconsin, Madison
pp. 208-222
Session 4: CMP Execution

Reunion: Complexity-Effective Multicore Redundancy (Abstract)

Babak Falsafi , Carnegie Mellon University
James C. Hoe , Carnegie Mellon University
Jared C. Smolens , Carnegie Mellon University
Brian T. Gold , Carnegie Mellon University
pp. 223-234

Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers (Abstract)

Mike Schlansker , Hewlett-Packard Laboratories, Palo Alto, California
Jean-Francois Collard , Hewlett-Packard Laboratories, Palo Alto, California
Jack Sampson , UC San Diego
Ruben Gonzalez , UPC Barcelona
Norman P. Jouppi , Hewlett-Packard Laboratories, Palo Alto, California
Brad Calder , UC San Diego
pp. 235-246

CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs (Abstract)

Olivier Temam , INRIA Futurs, France
Yves Lhuillier , LRI, University of Paris Sud, France
Pierre Palatin , INRIA Futurs, France
pp. 247-258

Support for High-Frequency Streaming in CMPs (Abstract)

Adam Stoler , Princeton University
Neil Vachharajani , Princeton University
George Z. N. Cai , Intel Corporation, Hillsboro, OR
Guilherme Ottoni , Princeton University
David I. August , Princeton University
Ram Rangan , Princeton University
pp. 259-272
Session 5A: Memory Dependences

Fire-and-Forget: Load/Store Scheduling with No Store Queue at All (Abstract)

Gabriel H. Loh , Georgia Institute of Technology
Samantika Subramaniam , Georgia Institute of Technology
pp. 273-284

NoSQ: Store-Load Communication without a Store Queue (Abstract)

Tingting Sha , University of Pennsylvania
Amir Roth , University of Pennsylvania
Milo M. K. Martin , University of Pennsylvania
pp. 285-296

DMDC: Delayed Memory Dependence Checking through Age-Based Filtering (Abstract)

Francisco Tirado , University Complutense of Madrid
Fernando Castro , University Complutense of Madrid
Manuel Prieto , University Complutense of Madrid
Luis Pinuel , University Complutense of Madrid
Michael Huang , University of Rochester
Daniel Chaver , University Complutense of Madrid
pp. 297-308
Session 5B: Networks and Coherence

Coherence Ordering for Ring-based Chip Multiprocessors (Abstract)

Michael R. Marty , University of Wisconsin, Madison
Mark D. Hill , University of Wisconsin, Madison
pp. 309-320

In-Network Cache Coherence (Abstract)

Li Shang , Queen?s University
Noel Eisley , Princeton University
Li-Shiuan Peh , Princeton University
pp. 321-332

ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers (Abstract)

Chita R. Das , University Park, PA 16802, USA
Chrysostomos A. Nicopoulos , University Park, PA 16802, USA
Dongkook Park , University Park, PA 16802, USA
N. Vijaykrishnan , University Park, PA 16802, USA
Mazin S. Yousif , Intel Corp., Hillsboro, OR
Jongman Kim , University Park, PA 16802, USA
pp. 333-346
Session 6A: Power

An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget (Abstract)

Alper Buyuktosunoglu , IBM T.J. Watson Research Center, NY
Chen-Yong Cher , IBM T.J. Watson Research Center, NY
Canturk Isci , IBM T.J. Watson Research Center, NY
Margaret Martonosi , Princeton University
Pradip Bose , IBM T.J. Watson Research Center, NY
pp. 347-358

Dynamic Standby Prediction for Leakage Tolerant Microprocessor Functional Units (Abstract)

Mohamed Elmasry , University of Waterloo
Ahmed Youssef , University of Waterloo
Mohab Anis , University of Waterloo
pp. 371-384
Session 6B: Caches and Prefetching

Adaptive Caches: Effective Shaping of Cache Behavior to Workloads (Abstract)

Gabriel H. Loh , Georgia Institute of Technology
Ranjith Subramanian , Georgia Institute of Technology
Yannis Smaragdakis , University of Oregon
pp. 385-396

Memory Prefetching Using Adaptive Stream Detection (Abstract)

Calvin Lin , University of Texas at Austin
Ibrahim Hur , University of Texas at Austin
pp. 397-408

Scalable Cache Miss Handling for High Memory-Level Parallelism (Abstract)

Josep Torrellas , University of Illinois at Urbana-Champaign
Luis Ceze , University of Illinois at Urbana-Champaign
James Tuck , University of Illinois at Urbana-Champaign
pp. 409-422
Session 7: Managing CMP Caches

Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions (Abstract)

Amrutur Bharadwaj , Indian Institute of Science Bangalore, India
Srihari Makineni , Intel Corporation, Hilsboro, Oregon
Ravi Iyer , Intel Corporation, Hilsboro, Oregon
S.K. Nandy , Indian Institute of Science Bangalore, India
Keshavan Varadarajan , Indian Institute of Science Bangalore, India
Donald Newell , Intel Corporation, Hilsboro, Oregon
Vishal Sharda , Indian Institute of Science Bangalore, India
pp. 433-442

ASR: Adaptive Selective Replication for CMP Caches (Abstract)

Bradford M. Beckmann , Microsoft Corporation
David A. Wood , University of Wisconsin, Madison
Michael R. Marty , University of Wisconsin, Madison
pp. 443-454

Managing Distributed, Shared L2 Caches through OS-Level Page Allocation (Abstract)

Lei Jin , University of Pittsburgh
Sangyeun Cho , University of Pittsburgh
pp. 455-468
Session 8: Technology-Driven Architecture

Die Stacking (3D) Microarchitecture (Abstract)

Bryan Black , Intel Corporation
Sadasivan Shankar , Intel Corporation
Murali Annavaram , Intel Corporation
Gabriel H. Loh , Intel Corporation
Paul Reed , Intel Corporation
John DeVale , Intel Corporation
Pat Morrow , Intel Corporation
Don McCaule , Intel Corporation
Daniel Pantuso , Intel Corporation
Ned Brekelbaum , Intel Corporation
Donald W. Nelson , Intel Corporation
Jeff Rupley , Intel Corporation
Lei Jiang , Intel Corporation
John Shen , Intel Corporation
Clair Webb , Intel Corporation
pp. 469-479

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor (Abstract)

Sadia Sharif , University of Texas at Austin
Nitya Ranganathan , University of Texas at Austin
Doug Burger , University of Texas at Austin
Karthikeyan Sankaralingam , University of Texas at Austin
Premkishore Shivakumar , University of Texas at Austin
Robert McDonald , University of Texas at Austin
Stephen W. Keckler , University of Texas at Austin
Haiming Liu , University of Texas at Austin
Paul Gratz , University of Texas at Austin
Ramadass Nagarajan , University of Texas at Austin
Simha Sethumadhavan , University of Texas at Austin
Heather Hanson , University of Texas at Austin
Saurabh Drolia , University of Texas at Austin
Rajagopalan Desikan , University of Texas at Austin
Changkyu Kim , University of Texas at Austin
Divya Gulati , University of Texas at Austin
M.S. Govindan , University of Texas at Austin
pp. 480-491

Leveraging Optical Technology in Future Bus-based Chip Multiprocessors (Abstract)

Matthew A. Watkins , Cornell University
Jose F. Martinez , Cornell University
Meyrem Kirman , Cornell University
Alyssa B. Apsel , Cornell University
David H. Albonesi , Cornell University
Rajeev K. Dokania , Cornell University
Nevin Kirman , Cornell University
pp. 492-503
Author Index

Author Index (PDF)

pp. 515
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