The Community for Technology Leaders
RSS Icon
Subscribe
Orlando, Florida, USA
Dec. 9, 2006 to Dec. 13, 2006
ISBN: 0-7695-2732-9
pp: 309-320
ABSTRACT
Ring interconnects may be an attractive solution for future chip multiprocessors because they can enable faster links than buses and simpler switches than arbitrary switched interconnects. Moreover, a ring naturally orders requests sufficiently to enable directory-less coherence, but not in the total order that buses provide for snooping coherence. Existing cache coherence protocols for rings either establish a (total) ordering point (ORDERING-POINT) or use a greedy order (GREEDY-ORDER) with unbounded retries. In this work, we propose a new class of ring protocols, RING-ORDER, in which requests complete in ring position order to achieve two benefits. First, RING-ORDER improves performance relative to ORDERING-POINT by activating requests immediately instead of waiting for them to reach the ordering point. Second, it improves performance stability relative to GREEDY-ORDER by not using retries. Thus, the new RING-ORDER combines the best of ORDERING-POINT (good performance stability) with the best of GREEDY-ORDER (good average performance)
INDEX TERMS
Protocols, Wires, Network topology, Sun, Delay, Stability, Coherence, Bandwidth, Costs, Switches,
CITATION
"Coherence Ordering for Ring-based Chip Multiprocessors", MICRO, 2006, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture 2006, pp. 309-320, doi:10.1109/MICRO.2006.14
SEARCH
35 ms
(Ver 2.0)

Marketing Automation Platform Marketing Automation Tool