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2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (2005)
Barcelona, Spain
Nov. 12, 2005 to Nov. 16, 2005
ISBN: 0-7695-2440-0
TABLE OF CONTENTS
Introduction
Cover
Keynote I
Session I: Register File and Memory System

How to Fake 1000 Registers (Abstract)

Trevor Mudge , University of Michigan, Ann Arbor
Steven K. Reinhardt , University of Michigan, Ann Arbor
Nathan L. Binkert , University of Michigan, Ann Arbor
David W. Oehmke , University of Michigan, Ann Arbor
pp. 7-18

Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows (Abstract)

Gary Tyson , Florida State University
David Whalley , Florida State University
Stephen Hines , Florida State University
pp. 19-29

Efficient Use of Invisible Registers in Thumb Code (Abstract)

Rajiv Gupta , University of Arizona
Arvind Krishnaswamy , University of Arizona
pp. 30-42
Session II: Processor Design and Optimization

A Criticality Analysis of Clustering in Superscalar Processors (Abstract)

Craig Zilles , University of Illinois at Urbana-Champaign
Pierre Salverda , University of Illinois at Urbana-Champaign
pp. 55-66

Incremental Commit Groups for Non-Atomic Trace Processing (Abstract)

Matt T. Yourst , State University of New York at Binghamton
Kanad Ghose , State University of New York at Binghamton
pp. 67-80
Session III: Multithreading / CMP

Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor (Abstract)

Santosh G. Abraham , Sun Microsystems Inc.
Khoa Nguyen , Sun Microsystems Inc.
Wei-Chung Hsu , University of Minnesota, Twin Cities
Abhinav Das , University of Minnesota, Twin Cities
Jiwei Lu , University of Minnesota, Twin Cities
pp. 93-104

Automatic Thread Extraction with Decoupled Software Pipelining (Abstract)

Ram Rangan , Princeton University
Guilherme Ottoni , Princeton University
Adam Stoler , Princeton University
David I. August , Princeton University
pp. 105-118
Session IV: Compilers and Dynamic Optimization

Continuous Path and Edge Profiling (Abstract)

Michael D. Bond , University of Texas at Austin
Kathryn S. McKinley , University of Texas at Austin
pp. 130-140

Improving Region Selection in Dynamic Optimization Systems (Abstract)

David Hiniker , Microsoft Corporation
Michael D. Smith , Harvard University
Kim Hazelwood , University of Virginia
pp. 141-154
Keynote II
Session V: Memory Disambiguation and Optimization

Scalable Store-Load Forwarding via Store Queue Index Prediction (Abstract)

Tingting Sha , University of Pennsylvania
Milo M.K. Martin , University of Pennsylvania
Amir Roth , University of Pennsylvania
pp. 159-170

Address-Indexed Memory Disambiguation and Store-to-Load Forwarding (Abstract)

Sam S. Stone , University of Illinois, Urbana-Champaign
Kevin M. Woley , University of Illinois, Urbana-Champaign
Matthew I. Frank , University of Illinois, Urbana-Champaign
pp. 171-182

Store Memory-Level Parallelism Optimizations for Commercial Applications (Abstract)

Lawrence Spracklen , Sun Microsystems
Yuan Chou , Sun Microsystems
Santosh G. Abraham , Sun Microsystems
pp. 183-196
Session VI: Processor Design

A Mechanism for Online Diagnosis of Hard Faults in Microprocessors (Abstract)

Daniel J. Sorin , Computer Engineering, Duke University
Sule Ozev , Computer Engineering, Duke University
Fred A. Bower , Computer Science, Duke University
pp. 197-208

uComplexity: Estimating Processor Design Effort (Abstract)

Francisco J. Mesa-Martinez , University of California Santa Cruz
Jose Renau , University of California Santa Cruz
Cyrus Bazeghi , University of California Santa Cruz
pp. 209-218

Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System (Abstract)

Manjunath Kudlur , University of Michigan, Ann Arbor
Hyunchul Park , University of Michigan, Ann Arbor
Scott Mahlke , University of Michigan, Ann Arbor
Kevin Fan , University of Michigan, Ann Arbor
pp. 219-232
Session VII: Speculation

Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns (Abstract)

Yale N. Patt , University of Texas at Austin
Hyesoon Kim , University of Texas at Austin
Onur Mutlu , University of Texas at Austin
pp. 233-244

Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors (Abstract)

Nevin K? , Cornell University
Jose F. Mart? , Cornell University
Meyrem K? , Cornell University
pp. 245-256

ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing (Abstract)

Smruti R. Sarangi , University of Illinois at Urbana-Champaign
Wei Liu, Josep Torrellas , University of Illinois at Urbana-Champaign
Yuanyuan Zhou , University of Illinois at Urbana-Champaign
pp. 257-270
Session VIII: Power, Temperature and Fault Management

A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance (Abstract)

Douglas W. Clark , Princeton University
V.J. Reddi , Univ. of Colorado at Boulder
David Brooks , Harvard University
Jin Lee , 3Programming Systems Lab, Corporate Tech. Group, Intel Corporation
Youfeng Wu , 3Programming Systems Lab, Corporate Tech. Group, Intel Corporation
Qiang Wu , Princeton University
Dan Connors , Univ. of Colorado at Boulder
Margaret Martonosi , Princeton University
pp. 271-282

Thermal Management of On-Chip Caches Through Power Density Minimization (Abstract)

Serkan Ozdemir , Northwestern University
Yehea Ismail , Northwestern University
Gokhan Memik , Northwestern University
Ja Chun Ku , Northwestern University
pp. 283-293

A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation (Abstract)

Tzvetan S. Metodi , University Of California at Davis
Andrew W. Cross , Massachusetts Institute of Technology
Darshan D. Thaker , University Of California at Davis
pp. 305-318
Session IX: Processor Architecture and Programming

"Flea-flicker" Multipass Pipelining: An Alternative to the High-Power Out-of-Order Offense (Abstract)

Ronald D. Barnes , George Mason University
Wen-mei W. Hwu , University of Illinois at Urbana-Champaign
Shane Ryoo , University of Illinois at Urbana-Champaign
pp. 319-330

The TM3270 Media-Processor (Abstract)

Hans van Antwerpen , Philips Semiconductors
Stamatis Vassiliadis , Delft, the Netherlands
Jan-Willem van de Waerdt , Philips Semiconductors
Sanjeev Das , Philips Semiconductors
Pedro Rodriguez , Philips Semiconductors
Sebastian Mirolo , Philips Semiconductors
Kulbhushan Kalra , Philips Semiconductors
Carlos Basto , Philips Semiconductors
Dinesh Amirtharaj , Philips Semiconductors
Jean-Paul van Itegem , Philips Semiconductors
Bill Zhong , Philips Semiconductors
Chris Yen , Philips Semiconductors
pp. 331-342

Stream Programming on General-Purpose Processors (Abstract)

Mendel Rosenblum , Stanford University
Jayanth Gummaraju , Stanford University
pp. 343-354

Shader Performance Analysis on a Modern GPU Architecture (Abstract)

Jordi Roca , Universitat Polit?cnica de Catalunya
Roger Espasa , Universitat Polit?cnica de Catalunya
Agustin Fernandez , Universitat Polit?cnica de Catalunya
Victor Moya , Universitat Polit?cnica de Catalunya
Carlos Gonzalez , Universitat Polit?cnica de Catalunya
pp. 355-364
Author Index

Author Index (PDF)

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