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38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05) (2005)
Barcelona, Spain
Nov. 12, 2005 to Nov. 16, 2005
ISBN: 0-7695-2440-0
pp: 30-42
Arvind Krishnaswamy , University of Arizona
Rajiv Gupta , University of Arizona
<p>The ARM processor is a dual width ISA processor that provides a 16-bit Thumb instruction set in addition to the 32-bit ARM instruction set. The compromises made in designing the Thumb instruction set leads to significantly increased instruction counts. This increase is in part due to the fact that only half of the register file is visible to most instructions in Thumb code. In this paper we address this inefficiency by providing a new instruction, the SetMask instruction, using which the compiler can change the visible subset of registers at any program point. Thus, through the use of this instruction the compiler can make use of all registers in all instructions. We present compiler techniques for allocating invisible registers and introducing SetMask instructions in a manner that the number of introduced instructions is minimized so that the increase in code size is insignificant. We implement this new instruction using the Dynamic Instruction Coalescing Framework which enables the SetMask instruction to have zero execution time cost. Our techniques eliminated 11.7% of MOV instructions from Thumb code while causing negligible code size increase.</p>

R. Gupta and A. Krishnaswamy, "Efficient Use of Invisible Registers in Thumb Code," 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05)(MICRO), Barcelona, Spain, 2005, pp. 30-42.
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